Memory device utilizing giant magnetoresistance effect

• US 6,055,179 A
• Filed: 05/17/1999
• Issued: 04/25/2000
• Est. Priority Date: 05/19/1998
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Nishimura, Naoki, Koganei, Akio
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/312,845
• Time in Patent Office: 344 Days
• Field of Search: 365/158, 365/171, 365/173, 365/157, 360/113, 360/119
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A memory device using giant magnetoresistance (GMR) effect, and an inexpensive memory device that has low power consumption, excels in memory performance, and is suitable for use in computer peripherals.

The memory device utilizes giant magnetoresistance effect and includes a substrate with an insulating surface; a monocrystalline semiconductor layer formed on the insulating surface of the substrate, a switching element formed at least on part of the monocrystalline semiconductor layer, a magnetoresistive film formed on the insulating surface of the substrate, the magnetoresistive film comprising a first magnetic layer and a second magnetic layer which has a higher coercive force than the first magnetic layer and which is stacked on the first magnetic layer with a non-magnetic layer interposed between them, and a word line installed near the magnetoresistive film with an insulating layer interposed between them, and the switching element is connected electrically to either the magnetoresistive film or word line.

Claims

1. A memory device utilizing giant magnetoresistance effect and comprising:

a substrate with an insulating surface;

a monocrystalline semiconductor layer formed on the insulating surface of said substrate;

a switching element formed at least on part of said monocrystalline semiconductor layer;

a magnetoresistive film formed on the insulating surface of said substrate, said magnetoresistive film consisting of a first magnetic layer and a second magnetic layer which has a higher coercive force than the first magnetic layer and which is stacked on the first magnetic layer with a non-magnetic layer interposed between them; and

a word line installed near said magnetoresistive film with an insulating layer interposed between them, wherein said switching element is connected electrically to either the magnetoresistive film or word line.

2. The memory device according to claim 1, wherein the thickness of said monocrystalline semiconductor layer is in the range of 50 to 500 nm.

3. The memory device according to claim 2, wherein the thickness of said monocrystalline semiconductor layer is in the range of 50 to 250 nm.

4. The memory device according to claim 3, wherein the thickness of said monocrystalline semiconductor layer is in the range of 60 to 120 nm.

5. The memory device according to claim 1, further comprising a buffer layer installed between the insulating surface of said substrate and magnetoresistive film.

6. The memory device according to claim 1, wherein said word line is installed between the insulating surface of said substrate and magnetoresistive film.

7. The memory device according to claim 1, further comprising a lower sense line installed between the insulating surface of said substrate and magnetoresistive film, and an upper sense line installed on said magnetoresistive film, wherein the non-magnetic layer of said magnetoresistive film is made of an insulating material.

8. The memory device according to claim 7, wherein said word line is installed on said upper sense line, separated by an insulating layer.

9. The memory device according to claim 7, wherein the thickness of said lower sense line is in the range of 1 to 50 nm.

10. The memory device according to claim 9, wherein the thickness of said lower sense line is in the range of 5 to 20 nm.

11. The memory device according to claim 7, wherein said lower sense line is formed by impurity doping on part other than the part where the switching element of said monocrystalline semiconductor layer is formed.

12. The memory device according to claim 1, wherein said substrate with an insulating surface comprises a SiO₂ layer formed on a silicon substrate.

13. The memory device according to claim 12, wherein said monocrystalline semiconductor layer comprises a monocrystalline silicon layer formed on said SiO₂ layer.

14. The memory device according to claim 1, wherein said switching element comprises a field-effect transistor comprising a source region, gate region, and drain region.

15. The memory device according to claim 1, further comprising magnetic-field concentrating layers made of a high-permeability material and installed near said magnetoresistive film to concentrate the magnetic field generated by the word line thereto.

16. A memory device utilizing giant magnetoresistance effect and comprising:

a substrate with an insulating surface;

a monocrystalline semiconductor layer formed on the insulating surface of said substrate;

N magnetoresistive films (N is an integer equal to or larger than

     2) installed on said insulating surface, and extending linearly in a first direction and arranged in parallel to one another in a second direction orthogonal to the first direction, said magnetoresistive films consisting of a first magnetic layer and a second magnetic layer which has a higher coercive force than the first magnetic layer and which is stacked on the first magnetic layer with a non-magnetic layer interposed between them;

M word lines (M is an integer equal to or larger than

     2) installed near said magnetoresistive films, separated by an insulating layer, and extending linearly in the second direction and arranged in parallel to one another in the first direction;

N first switching elements formed at least on part of said monocrystalline semiconductor layer and electrically connected, respectively, to said N magnetoresistive films; and

M second switching elements formed at least on part of said monocrystalline semiconductor layer and electrically connected, respectively, to said M word lines.

18. The memory device according to claim 16 or claim 17, wherein the thickness of said monocrystalline semiconductor layer is in the range of 50 to 500 nm.

19. The memory device according to claim 18, wherein the thickness of said monocrystalline semiconductor layer is in the range of 50 to 250 nm.

20. The memory device according to claim 19, wherein the thickness of said monocrystalline semiconductor layer is in the range of 60 to 120 nm.

21. The memory device according to claim 16 or claim 17, further comprising a buffer layer installed between the insulating surface of said substrate and magnetoresistive films.

22. The memory device according to claim 16 or 17, wherein said word lines are installed between the insulating surface of said substrate and magnetoresistive films.

29. The memory device according to claim 16 or claim 17, wherein said substrate with an insulating surface comprises a SiO₂ layer formed on the surface of a silicon substrate.

30. The memory device according to claim 29, wherein said monocrystalline semiconductor layer comprises a monocrystalline silicon layer formed on said SiO₂ layer.

31. The memory device according to claim 16 or claim 17, wherein each of said first and second switching elements comprises a field-effect transistor comprising a source region, gate region, and drain region.

32. The memory device according to claim 16 or claim 17, further comprising:

magnetic-field concentrating layers made of a high-permeability material and installed near said magnetoresistive films to concentrate the magnetic fields generated by the word lines thereto.

17. A memory device utilizing giant magnetoresistance effect and comprising:

a substrate with an insulating surface;

a monocrystalline semiconductor layer formed on the insulating surface of said substrate;

memory cells consisting of magnetoresistive films arranged in an M×

N matrix installed on the insulating surface of said substrate (M and N are integers equal to or larger than

     2), each of said memory cells consisting of a first magnetic layer and a second magnetic layer which has a higher coercive force than the first magnetic layer and which is stacked on the first magnetic layer with a non-magnetic layer interposed between them;

N sense lines extending linearly in a first direction and arranged in parallel to one another in a second direction orthogonal to the first direction, and electrically connected, respectively, to M memory cells arranged in parallel to one another in the first direction;

M word lines installed near each of said memory cells, separated by an insulating layer, and extending linearly in the second direction and arranged in parallel to one another in the first direction;

N first switching elements formed at least on part of said monocrystalline semiconductor layer and electrically connected, respectively, to said N sense lines; and

M second switching elements formed at least on part of said monocrystalline semiconductor layer and electrically connected, respectively, to said M word lines.

23. The memory device according to claim 17, wherein said N sense lines are installed between the memory cells in such a way as to tie, respectively, the M memory cells arranged in parallel to one another in the first direction.

24. The memory device according to claim 17, wherein said N sense lines consist of lower sense lines installed between the insulating surface of said substrate and magnetoresistive films, and further comprises M upper sense lines extending linearly in the second direction and arranged in parallel to one another in the first direction, and electrically connected, respectively, to N memory cells arranged in parallel to one another in the second direction, wherein the non-magnetic layer of said magnetoresistive films is made of an insulating material.

25. The memory device according to claim 24, wherein said M word lines are installed on said M upper sense lines, respectively, via an insulating layer.

26. The memory device according to claim 24, wherein the thickness of the film in said lower sense lines are in the range of 1 to 50 nm.

27. The memory device according to claim 26, wherein the thickness of the film in said lower sense lines are in the range of 5 to 20 nm.

28. The memory device according to claim 24, wherein said lower sense lines are formed by impurity doping on part of said monocrystalline semiconductor layer other than the part where the switching elements are formed.