Multi-bank architecture for a wide I/O DRAM

• US 6,055,202 A
• Filed: 08/03/1999
• Issued: 04/25/2000
• Est. Priority Date: 05/13/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US09/365,819
• Time in Patent Office: 266 Days
• Field of Search: 365/230.03, 365/230.06, 365/205, 365/51, 365/52, 365/63, 365/230.01
• US Class Current: 365/230.03
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An architecture for a multi-bank DRAM is described which utilizes banks which are staggered in order to increase the amount of data which can be accessed at any one time. The banks are staggered such that a portion of each bank is provided on opposite sides of a data path so that a single address can simultaneously specify both portions of the bank so that twice the amount of data can be accessed.

Claims

1. A memory circuit comprising:

a plurality of memory cells;

an input/output data path for data to be written into and read from said plurality of memory cells, said data path being provided such that a first portion of said memory cells is on a first side of said data path and a second different portion of said memory cells is on a second different side of said data path; and

accessing circuitry, said accessing circuitry simultaneously accessing said first and second portions of said memory cells in response to an input address signal.

2. The memory circuit of claim 1 wherein said accessing circuitry comprises:

a first accessing circuit located on said first side of said data path, said first accessing circuit accessing memory cells within said first portion of said memory cells; and

a second accessing circuit located on said second side of said data path, said second accessing circuit accessing memory cells within said second portion of said memory cells.

3. The memory circuit of claim 2 wherein said first and second accessing circuits comprises:

a row decoder, said row decoder addressing word lines of an associated portion of said memory cells;

a sense amplifier circuit, said sense amplifier sensing data bits on bit lines of an associated portion of said memory cells; and

a column decoder, said column decoder commonly addressing the bit lines of an associated portion of said memory cells.

4. The memory circuit of claim 1 wherein said plurality of memory cells are arranged into at least a first bank of memory cells and a second bank of memory cells, each of said banks of memory cells having memory cells in said first and second portions of said memory cells.

5. The memory circuit of claim 4 wherein said accessing circuitry accesses only one of said banks of memory cells when simultaneously accessing said first and second portions of said memory cells in response to an input address signal.

6. The memory circuit of claim 5 wherein a number of banks is two and each bank is further divided into at least a first sub bank located on said first side of said data path and a second sub bank located on said second side of said data path.

7. A memory device comprising:

a plurality of memory cells;

a data path for data to be written into and read from said plurality of memory cells, said data path being provided such that a first portion of said memory cells is on a first side of said data path and a second different portion of said memory cells is on a second different side of said data path; and

means for simultaneously writing information from said data path into said first and second portions of said memory cells and for simultaneously writing data from said first and second portions of said memory cells into said data path in response to a single address signal.

8. The memory device of claim 7 wherein said simultaneously writing means comprises:

a first accessing circuit located on said first side of said data path, said first accessing circuit accessing memory cells within said first portion of said memory cells; and

a second accessing circuit located on said second side of said data path, said second accessing circuit accessing memory cells within said second portion of said memory cells.

9. The memory device of claim 8 wherein said first and second accessing circuits comprises:

a row decoder, said row decoder addressing word lines of an associated portion of said memory cells;

a sense amplifier circuit, said sense amplifier sensing data bits on bit lines of an associated portion of said memory cells; and

a column decoder, said column decoder commonly addressing the bit lines of an associated portion of said memory cells.

10. The memory device of claim 7 wherein said plurality of memory cells are arranged into at least a first bank of memory cells and a second bank of memory cells, each of said banks of memory cells having memory cells in said first and second portions of said memory cells.

11. The memory device of claim 10 wherein said writing means accesses only one of said banks of memory cells in response to an input address signal.

12. The memory device of claim 11 wherein a number of banks is two and each bank is further divided into at least a first sub bank located on said first side of said data path and a second sub bank located on said second side of said data path.

13. A processor based system comprising:

a processor; and

a memory circuit operating in cooperation with said processor, said memory circuit comprising;

a plurality of memory cells;

an input/output data path for data to be written into and read from said plurality of memory cells, said data path being provided such that a first portion of said memory cells is on a first side of said data path and a second different portion of said memory cells is on a second different side of said data path; and

accessing circuitry, said accessing circuitry simultaneously accessing said first and second portions of said memory cells in response to an input address signal.

14. The system of claim 13 wherein said accessing circuitry comprises:

a first accessing circuit located on said first side of said data path, said first accessing circuit accessing memory cells within said first portion of said memory cells; and

a second accessing circuit located on said second side of said data path, said second accessing circuit accessing memory cells within said second portion of said memory cells.

15. The system of claim 14 wherein said first and second accessing circuits comprises:

a row decoder, said row decoder addressing word lines of an associated portion of said memory cells;

a sense amplifier circuit, said sense amplifier sensing data bits on bit lines of an associated portion of said memory cells; and

a column decoder, said column decoder commonly addressing the bit lines of an associated portion of said memory cells.

16. The system of claim 13 wherein said plurality of memory cells are arranged into at least a first bank of memory cells and a second bank of memory cells, each of said banks of memory cells having memory cells in said first and second portions of said memory cells.

17. The system of claim 16 wherein said accessing circuitry accesses only one of said banks of memory cells when simultaneously accessing said first and second portions of said memory cells in response to an input address signal.

18. The system of claim 17 wherein a number of banks is two and each bank is further divided into at least a first sub bank located on said first side of said data path and a second sub bank located on said second side of said data path.

19. A processor based system comprising:

a processor; and

a memory device coupled to said processor, said memory device comprising;

a plurality of memory cells;

a data path for data to be written into and read from said plurality of memory cells, said data path being provided such that a first portion of said memory cells is on a first side of said data path and a second different portion of said memory cells is on a second different side of said data path; and

means for simultaneously writing information from said data path into said first and second portions of said memory cells and for simultaneously writing data from said first and second portions of said memory cells into said data path in response to a single address signal.

20. The system of claim 19 wherein said simultaneously writing means comprises:

a first accessing circuit located on said first side of said data path, said first accessing circuit accessing memory cells within said first portion of said memory cells; and

a second accessing circuit located on said second side of said data path, said second accessing circuit accessing memory cells within said second portion of said memory cells.

21. The system of claim 20 wherein said first and second accessing circuits comprises:

a row decoder, said row decoder addressing word lines of an associated portion of said memory cells;

a sense amplifier circuit, said sense amplifier sensing data bits on bit lines of an associated portion of said memory cells; and

a column decoder, said column decoder commonly addressing the bit lines of an associated portion of said memory cells.

22. The system of claim 19 wherein said plurality of memory cells are arranged into at least a first bank of memory cells and a second bank of memory cells, each of said banks of memory cells having memory cells in said first and second portions of said memory cells.

23. The system of claim 22 wherein said writing means accesses only one of said banks of memory cells in response to an input address signal.

24. The system of claim 23 wherein a number of banks is two and each bank is further divided into at least a first sub bank located on said first side of said data path and a second sub bank located on said second side of said data path.

25. A method of operating a memory circuit comprising the steps of:

generating an address signal for the memory circuit, the address signal specifying locations of a first portion of memory cells located on a first side of a data path circuit within the circuit and a second different portion of memory cells located on a second different side of the data path circuit within the memory circuit;

simultaneously addressing the first and second portions of memory cells in response to the address signal; and

transmitting data between the first and second portions and the data path circuit.

26. The method of claim 25 wherein an amount of data transmitted between the first portion and the data path circuit is the same as an amount of data transmitted between the second portion and the data path circuit.

27. The method of claim 25 wherein the memory circuit is organized into at least a first and second bank of memory cells and said addressing step addresses only one bank when simultaneously addressing the first and second portions of memory cells in response to the address signal.

28. A method of operating a memory circuit comprising the steps of:

receiving an address signal for the memory circuit, the address signal specifying locations of a first portion of memory cells located on a first side of a data path circuit within the circuit and a second different portion of memory cells located on a second different side of the data path circuit within the memory circuit;

simultaneously accessing the first and second portions of memory cells in response to the address signal; and

transmitting data between the first and second portions and the data path circuit.

29. The method of claim 28 wherein an amount of data transmitted between the first portion and the data path circuit is the same as an amount of data transmitted between the second portion and the data path circuit.

30. The method of claim 28 wherein the memory circuit is organized into at least a first and second bank of memory cells and said accessing step accesses only one bank when simultaneously accessing the first and second portions of memory cells in response to the address signal.