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Synchronous semiconductor memory device exhibiting an operation synchronous with an externally inputted clock signal

  • US 6,055,209 A
  • Filed: 06/29/1998
  • Issued: 04/25/2000
  • Est. Priority Date: 06/27/1997
  • Status: Expired due to Term
First Claim
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1. A synchronous semiconductor memory device comprising:

  • a command decoder;

    a row address control circuit provided with command signal inputs from said command decoder;

    a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronism with an externally inputted clock signal, an internal command signal having been generated in synchronism with the externally inputted clock signal, said internal command signal being provided as a direct input to said row address control circuit,wherein said pseudo internal command signal generator comprises a test mode signal connector and a tester circuit for generating the pseudo internal command signal in accordance with the internal control signal.

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