Synchronous semiconductor memory device exhibiting an operation synchronous with an externally inputted clock signal
First Claim
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1. A synchronous semiconductor memory device comprising:
- a command decoder;
a row address control circuit provided with command signal inputs from said command decoder;
a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronism with an externally inputted clock signal, an internal command signal having been generated in synchronism with the externally inputted clock signal, said internal command signal being provided as a direct input to said row address control circuit,wherein said pseudo internal command signal generator comprises a test mode signal connector and a tester circuit for generating the pseudo internal command signal in accordance with the internal control signal.
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Abstract
A synchronous semiconductor memory device has a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronizing with an externally inputted clock signal, an internal command signal having been generated in synchronizing with the externally inputted clock signal.
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Citations
10 Claims
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1. A synchronous semiconductor memory device comprising:
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a command decoder; a row address control circuit provided with command signal inputs from said command decoder; a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronism with an externally inputted clock signal, an internal command signal having been generated in synchronism with the externally inputted clock signal, said internal command signal being provided as a direct input to said row address control circuit, wherein said pseudo internal command signal generator comprises a test mode signal connector and a tester circuit for generating the pseudo internal command signal in accordance with the internal control signal. - View Dependent Claims (2, 3)
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4. A synchronous semiconductor memory device provided with a pseudo internal command signal generator for generating a pseudo internal command signal which controls, in non-synchronism with an externally inputted clock signal, an internal command signal having been generated in synchronism with an externally inputted clock signal, said internal command signal being provided as an input to a row address control signal generator to reset an output signal of said row address control signal,
wherein the pseudo internal command signal is generated by a circuit having a test mode signal input into an internal control signal in non-synchronism with the clock signal without being input into a command decoder for receiving a normal input signal and outputting a synchronous signal with the clock signal.
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7. A synchronous semiconductor memory comprising:
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a command decoder with outputs providing first and second internal command signals; a row address control circuit with first, second, and third inputs accepting the first and second internal command signals and a third internal command signal respectively; a pseudo internal command signal generator for generating a pseudo internal command signal serving as the third internal command signal, the third internal command signal controlling said row address control circuit non-synchronously with an externally inputted clock signal, the third internal command signal having been generated in synchronism with the externally inputted clock signal, wherein said pseudo internal command signal generator comprises a first input signal terminal feeding a first invertor, and an output of said first invertor serving as the third internal command signal, said pseudo internal command signal generator further comprises a second input terminal feeding said first invertor via a NAND gate and a delay circuit, and said pseudo internal command signal generator further comprises a third input terminal feeding said first invertor via said NAND gate. - View Dependent Claims (8, 9, 10)
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Specification