Method and apparatus for fast acquisition and multipath search in a spread spectrum system

• US 6,055,264 A
• Filed: 08/01/1997
• Issued: 04/25/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Fees

• Current Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Chowdhury, Afsar, Kenney, Thomas
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Burd, Kevin M
• Application Number:
  US08/904,897
• Time in Patent Office: 998 Days
• Field of Search: 375/206, 375/208, 375/209, 375/210, 375/142, 375/145, 375/149, 375/150, 708/422, 708/813
• US Class Current: 375/150
• CPC Class Codes: H04B 1/70775 Multi-dwell schemes, i.e. multiple accumulation times

Abstract

Early and on-time signals are generated from a received CDMA signal for each PN code phase being searched, and the early and on-time signals are each divided into a number of subdwells sequentially in time. A correlation is then performed for each PN code phase search, on subdwells of the early and on-time signals for that PN code phase in a staggered manner in time, by alternating the correlation between the early and on-time signals during each sequential subdwell correlation. A detection statistic for the PN code phase is then generated from the correlation result. In an embodiment of the invention, two PN code phases are searched simultaneously by staggering the subdwell correlations in an alternate fashion between the early and on-time signals, so that each PN code phase uses a different set of subdwell correlations. In an alternative embodiment, a single PN code phase is searched by alternating the correlation between the early and on-time signals during each sequential subdwell correlation.

Claims

1. A method for searching for a direct sequence spread spectrum (DS-SS) signal, said method comprising the steps of:

(a) receiving a first signal, said first signal spread by at least a PN code sequence having a chip period;

(b) generating a second signal from said first signal, said second signal being a digital signal;

(c) generating a third signal from said first signal, said third signal being a digital signal spaced a predetermined portion of said chip period in phase from said second signal;

(d) generating said PN code sequence at a first phase;

(e) defining a correlation period and dividing each of said second and third signals into a first and second plurality of N subdwells, respectively, within said correlation period, wherein the N subdwells included in each of said first and second plurality of N subdwells are sequential in time, and wherein an x^th subdwell of said first plurality of N subdwells, and an x^th subdwell of said second plurality of N subdwells are substantially concurrent in time;

(f) correlating said second signal with at least said PN code sequence at said first phase over a z^th subdwell of said first plurality of N subdwells to generate a first phase correlation result for the z^th subdwell of said first plurality of N subdwells;

(g) correlating said third signal with at least said PN code sequence at said first phase over a (z+1 )^th subdwell of said second plurality of N subdwells to generate a first phase correlation result for the (z+1 )^th subdwell of said second plurality of subdwells;

(h) repeating steps f and g, increasing the value of z by at least 2 for each repetition of both steps and storing the first phase correlation result for each repetition of steps f and g, until the end of said correlation period has been reached; and

(i) generating a detection statistic for said PN code sequence at said first phase from the first phase correlation results of steps f, g, and h.

2. The method of claim 1, wherein step (i) comprises computing an FFT from the first phase correlation results of steps f, g, and h.

3. The method of claim 1, wherein step (i) comprises summing the first phase correlation results of steps f, g, and h.

4. The method of claim 1, wherein said second signal is spaced 1/2 of said chip period in phase from said third signal.

5. The method of claim 4, wherein said PN code sequence has a chip rate of 1.2888 million chips per second.

6. The method of claim 5, wherein said correlation period equals 944 times said chip period and the number of subdwells in each of said first and second pluralities of subdwells equals 12.

7. The method of claim 1, wherein said step of generating said PN code sequence further comprises generating said PN code sequence at a second phase, wherein step f further comprises correlating said third signal with at least said PN code sequence at said second phase during a z^th subdwell of said second plurality of N subdwells to generate a second phase correlation result for the z^th subdwell of said second plurality of N subdwells, wherein step g further comprises correlating said second signal with at least said PN code sequence at said second phase during a (z+1)^th subdwell of said first plurality of subdwells to generate a second phase correlation result for the (z+1)^th subdwell of said first plurality of subdwells, wherein step h further comprises storing the second phase correlation result for each repetition of steps f and g, and wherein step i further comprises generating a detection statistic for said PN code sequence at said second phase from the second phase correlation results of steps f, g, and h.

8. The method of claim 7, wherein step i comprises computing an FFT from the results of the correlations performed in steps f, g, and h.

9. The method of claim 7, wherein step i comprises summing the results of the correlations performed in steps f, g, and h.

10. The method of claim 7, wherein said second signal is spaced 1/2 of said chip period in phase from said third signal.

11. The method of claim 10, wherein said PN code sequence has a chip rate of 1.2888 million chips per second.

12. The method of claim 11, wherein said correlation period 944 times said chip period and the number of subdwells in each of said first and second pluralities of subdwells equals 12.

13. An apparatus for searching for a CDMA signal, said apparatus comprising:

a receiver for receiving a first signal, said first signal spread by a PN code sequence having a chip period;

a converter for converting said first signal into a second and a third signal, said second and third signals being digital signals spaced a predetermined portion of said chip period apart in phase;

a PN code generator for generating said PN code sequence at a first phase;

first control circuitry for defining a correlation period and dividing each of said second and third signals into a first and second plurality of N subdwells, respectively, within said correlation period, wherein the N subdwells included in each of said first and second plurality of N subdwells are sequential in time, and wherein the x^th subdwell of said first plurality and the x^th subdwell of said second plurality are substantially concurrent in time;

a correlator for correlating said second signal by at least said PN code sequence at said first phase over the z^th subdwell of said first plurality of N subdwells to generate a first phase correlation result for the z^th subdwell of said first plurality of subdwells, and further for correlating said third signal by at least said PN code sequence at said first phase over the (z+1)^th subdwell of said second plurality of subdwells to generate a first phase correlation result for the (z+1)^th subdwell of said second plurality of subdwells;

second control circuitry for causing said correlator to generate said first phase correlation result for the z^th subdwell of said first plurality of N subdwells and the (z+1)^th subdwell of said second plurality of N subdwells, for incrementing the value of z by at least 2, and for repeating the correlation of the z^th subdwell of said first plurality of N subdwells and the (z+1)^th subdwell of said second plurality of N subdwells until the end of said correlation period is reached;

a memory device for storing the first phase correlation results generated for each correlation performed in said correlator; and

third control circuitry for generating a detection statistic for said PN code sequence at said first phase, from the first phase correlation results stored in said memory device, when said multiplier has reached the end of said correlation period.

14. The apparatus of claim 13, wherein said third control circuitry comprises circuitry for computing an FFT from the first phase correlation results stored in said memory device to generate said detection statistic.

15. The apparatus of claim 13, wherein said third control circuitry comprises circuitry for summing the first phase correlation results stored in said memory device to generate said detection statistic.

16. The apparatus of claim 13, wherein said converter converts said first signal into a second and third signal spaced 1/2 of said chip period apart.

17. The apparatus of claim 16, wherein said PN code sequence has a chip rate of 1.2888 million chips per second.

18. The apparatus of claim 17, wherein said correlation period defined by said first control circuitry equals 944 times said chip period and the number of subdwells in each of said first and second pluralities of subdwells equals 12.

19. The apparatus of claim 13, wherein said PN code generator further generates said PN code sequence at a second phase, wherein said correlator further correlates said third signal with at least said PN code sequence at said second phase during the z^th subdwell of said second plurality of N subdwells to generate a second phase correlation result for the z^th subdwell of said second plurality of N subdwells, wherein said correlator further correlates said second signal with at least said PN code sequence at said second phase during a (z+1 )th subdwell of said first plurality of N subdwells to generate a second phase correlation result for the (z+1 )th subdwell of said first plurality of N subdwells, wherein said second control circuitry further causes said correlator to generate said second phase correlation result for the z^th subdwell of said second plurality of N subdwells and the (z+1)th subdwell of said first plurality of N subdwells, to increment the value of z by at least 2, and to repeat the correlation and the increment of z until the end of said correlation period is reached, wherein said memory device further stores the second phase correlation results for each correlation performed in said correlator, and wherein said third control circuitry further generates a detection statistic for said PN code sequence at said second phase from the second phase correlation results stored in said memory device when said correlator has reached the end of said correlation period.

20. The apparatus of claim 19, wherein said third control circuitry further comprises circuitry for computing an FFT from the second phase correlation results stored in said memory device to generate said detection statistic for said PN code phase at said second phase.

21. The apparatus of claim 19, wherein said third control circuitry further sums the second phase correlation results stored in said memory device to generate said detection statistic for said PN code phase at said second phase.

22. The apparatus of claim 19, wherein said converter converts said first signal into a second and third signal spaced 1/2 of said chip period apart.

23. The apparatus of claim 22, wherein said chip period of said PN code sequence has a chip rate of 1.2888 million chips per second.

24. The apparatus of claim 23, wherein said correlation period defined by said first control circuitry equals 944 times said chip period and the number of subdwells in each of said first and second pluralities of subdwells equals 12.