Control system and method for semiconductor integrated circuit test process

• US 6,055,463 A
• Filed: 05/18/1998
• Issued: 04/25/2000
• Est. Priority Date: 05/20/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jae Young, Cheong, Kwang Yung, Lee, Ann Seong
• Primary Examiner(s): Ellis, Christopher P.
• Assistant Examiner(s): DILLON JR, JOSEPH A
• Application Number:
  US09/080,192
• Time in Patent Office: 708 Days
• Field of Search: 209/571, 209/573, 209/574, 702/81, 702/82, 702/83, 702/84, 395/500.05, 700/223
• US Class Current: 700/223
• CPC Class Codes: B07C 5/344 according to electric or electromagnetic properties sorting according to size measured electrically or electronically B07C5/08; material testing by magnetic means G01N24/00, G01N27/00, by electrical means G01N27/00; electrical measuring devices in general G01R; coin testing G07D5/00
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G05B 2219/32218 Sort workpieces as function of quality data
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A test control system for controlling overall test procedures which processes test data generated from the final test process and analyzes bin category results. The control system uses testers for testing electrical characteristics of IC devices, a host computer for processing data transmitted from the testers and for creating a number of database structures, and distributed computers for monitoring the test progress and analyzing the test results using the database structures stored in the host computer. A control method using the control system includes the steps of: performing a final test as a lot; monitoring the status of the final test progress while storing test data during the final test; determining if the final test is completed; performing a lot decision after the final test is completed based on bin category limits; and displaying the lot decision result and storing the test data. The lot decision is based upon any bin category having a bin capacity exceeding its bin category limit by greater than a certain predetermined value even though the lot meets the yield requirement. As a result, the control system can detect an abnormal lot more easily than a system in which the lot decision is based only on yield.

Claims

1. A method of specifying quality assurance testing of integrated circuit devices, said method comprising the steps of:

loading a tester with a test program, and identifying IC devices to be tested by the tester by lot;

testing each of the IC devices of a said lot under a plurality of test sequences, and sorting the IC devices of the lot into bin categories according to results of the test sequences, the test sequences each defining a pass or fail standard for the IC devices;

monitoring progress of the testing of the lot of IC devices, while storing test result data indicative of the results of the test sequences;

establishing limits for each of the bin categories;

when the testing and sorting is completed, making a lot decision governing a subsequent test flow path of a tested lot by using the stored test result data and the bin category limits, said making of the lot decision including determining whether the lot meets a yield requirement of the test sequences;

storing the test result data in different memory locations in a computer in accordance with the lot decision, and displaying the lot decision; and

executing quality assurance test decisions when the lot meets the yield requirement, said quality assurance test decisions including;

if the tested lot has a quantity of IC devices exceeding the bin category limits, which quantity is equal to or greater than a predetermined number, then performing both a sampling test and a production reliability test on IC devices in the lot which have passed the test sequences,

if the tested lot has a quantity of IC devices exceeding the bin category limits, which quantity is less than the predetermined number, then performing only the sampling test only on the IC devices in the lot which have passed the test sequences, and

if the tested lot has no IC devices exceeding the bin category limits, then omitting the sampling test and the production reliability test.

2. The method as claimed in claim 1, wherein said monitoring of the progress of the testing of the lot of IC devices comprises analyzing data structures resident in the memory of the computer to make a determination of whether the testing of the IC devices is progressing normally according to predetermined criteria, the data structures containing data representing a tester name, a lot test start time, a lot size of IC devices, a total count of IC devices, a quantity of failed IC devices, a quantity of passed IC devices, a quantity of devices experiencing open/short failures, and a quantity of devices experiencing failures other than open/short failures;

and

producing an alarm message if analysis of the data structures determines that the testing of the IC devices is not progressing normally, otherwise, continuing the testing and sorting of the IC devices.

3. The method as claimed in claim 1, wherein the making of the lot decision and the storing of the test result data according to the lot decision comprises:

determining whether a yield of IC devices is equal to or greater than a predetermined value, and if not, storing the test result data into a no-go database;

determining if the yield exceeds 100% when the yield is equal to or greater than the predetermined value, and if so, storing the test result data into the no-go database and repeating said testing of the lot of IC devices;

if the yield is less than 100% but equal to or greater than the predetermined value, determining if there are any bin categories having their bin category limits exceeded;

storing the test result data into the no-go database and requesting an incoming inspection when any bin categories having their bin category limits exceeded are found; and

storing the test result data into a go database and requesting an incoming inspection when no bin categories exceeding their bin category limits are found.

4. The method as claimed in claim 1, wherein the making of the lot decision and the storing of the test result data in accordance with the lot decision comprises:

determining whether a yield of IC devices is equal to or greater than a predetermined value, and if not, storing the test result data into a no-go database;

determining if the yield exceeds 100% when the yield is equal to or greater than the predetermined value, and if so, storing the test result data into the no-go database and performing a sampling test;

if the yield is less than 100% but equal to or greater than the predetermined value, determining if there are any bin categories having their bin category limits exceeded;

storing the test result data into the no-go database and requesting an incoming inspection when any bin categories having their bin category limits exceeded are found; and

storing the test result data into a go database and requesting an incoming inspection when no bin categories having their bin category limits exceeded are found.

5. The method as claimed in claim 1, wherein the executing of quality assurance test decisions further comprises:

determining if the quantity of IC devices which have failed the test sequences is equal to or less than a second predetermined number when the yield exceeds 100%, and if so, performing a sampling test of a sample quantity of IC devices in the lot which have passed the test sequences, otherwise, repeating the test sequences on the IC devices.

6. The method as claimed in claim 1, wherein the establishing of the limits of the bin categories comprises:

testing a predetermined number of lots of IC devices and then calculating an average number `P` of IC devices sorted into each of the bin categories during the testing;

calculating a standard deviation `σ

=√

(P(1-P)/n` by using the average `P` and a lot size `n`;

determining if the average `P` is equal to or less than a first reference value;

determining if `P+3σ

` is equal to or less than a second reference value when the average `P` is equal to or less than the first reference value, and determining if the average `P` is equal to or less than a third reference value when the average `P` exceeds the first reference value;

setting a bin category limit as `P+3σ

` when `P+3σ

` exceeds the second reference value when the average `P` is equal to or less than the first reference value, setting a bin category limit as the second reference value when `P+3σ

` is equal to or less than the second reference value when the average `P` is equal to or less than the first reference value, and setting a bin category limit as `P+2σ

` when the average `P` exceeds the first reference value and is equal to or less than the third reference value;

determining if the average `P` is equal to or less than a fourth reference value when the average `P` exceeds the third reference value;

setting a bin category limit as `P+σ

` when the average `P` is equal to or less than the fourth reference value when the average `P` exceeds the third reference value;

determining if the average `P` is equal to or less than a fifth reference value when the average `P` exceeds the fourth reference value; and

setting a bin category limit as the average `P` when the average `P` is equal to or less than the fifth reference value when the average `P` exceeds the fourth reference value, and

setting no bin category limit when the average `P` exceeds the fifth reference value,

wherein the second reference value is less than the first reference value, the third reference value is greater than the first reference value, the fourth reference value is greater than the third reference value, and the fifth reference value is greater than the fourth reference value.

7. The method as claimed in claim 6, wherein the first reference value is 0.3% of the lot size and the second reference value is 0.2% of the lot size.

8. The method as claimed in claim 1, wherein the executing of quality assurance test decisions further comprises:

determining if the quantity of failed IC devices is equal to or less than a second predetermined number when the yield exceeds 100%, and if so, performing a sampling test of a first quantity of devices in the lot which have passed the test sequences, otherwise, performing a sampling test of a second quantity of IC devices in the lot which have passed the test sequences, the second quantity being twice the first quantity.

9. The method as claimed in claim 8, wherein the predetermined number is 5.