Processor local bus posted DMA FlyBy burst transfers
First Claim
1. A data transfer system for accomplishing data transfers in an information processing system, said data transfer system comprising:
- a peripheral device;
a first controller selectively coupled to said peripheral device;
a memory unit;
a primary bus;
a secondary bus connected between said peripheral device and said memory unit, said secondary bus being separate from said primary bus; and
a second controller connected to said first controller through said primary bus, said second controller being coupled to said memory unit, said second controller being selectively operable for controlling data transfers directly between said peripheral device and said memory unit over said secondary bus, said first controller being responsive to a data transfer request signal from said peripheral device for initiating a transfer cycle with said second controller, said second controller being responsive to said transfer cycle to selectively enable a data transfer directly between said memory unit and said peripheral device over said secondary bus, said second controller being operable to assert a transfer complete signal after said peripheral device acknowledges receipt of a transfer address, said transfer complete signal being operable to effect a release of said primary bus prior to a completion of said data transfer over said secondary bus.
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Abstract
A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.
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Citations
35 Claims
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1. A data transfer system for accomplishing data transfers in an information processing system, said data transfer system comprising:
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a peripheral device; a first controller selectively coupled to said peripheral device; a memory unit; a primary bus; a secondary bus connected between said peripheral device and said memory unit, said secondary bus being separate from said primary bus; and a second controller connected to said first controller through said primary bus, said second controller being coupled to said memory unit, said second controller being selectively operable for controlling data transfers directly between said peripheral device and said memory unit over said secondary bus, said first controller being responsive to a data transfer request signal from said peripheral device for initiating a transfer cycle with said second controller, said second controller being responsive to said transfer cycle to selectively enable a data transfer directly between said memory unit and said peripheral device over said secondary bus, said second controller being operable to assert a transfer complete signal after said peripheral device acknowledges receipt of a transfer address, said transfer complete signal being operable to effect a release of said primary bus prior to a completion of said data transfer over said secondary bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method for transferring data in an information processing system, said method comprising:
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receiving a data transfer request by a control device from a peripheral device, said peripheral device being coupled to a first bus; initiating a transfer cycle to transfer an address associated with said data transfer request to a memory unit coupled to a second bus, said second bus being arranged to directly connect said peripheral device and said memory unit; selectively enabling a data transfer directly between the memory unit and the peripheral device over said second bus; and releasing said first bus prior to a completion of said data transfer over said second bus. - View Dependent Claims (32, 33, 34, 35)
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Specification