Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches

• US 6,055,605 A
• Filed: 10/24/1997
• Issued: 04/25/2000
• Est. Priority Date: 10/24/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Steely, Simon C. Jr., Van Doren, Stephen R., Gharachorloo, Kourosh, Sharma, Madhumitra
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/957,544
• Time in Patent Office: 914 Days
• Field of Search: 711/130, 711/147, 711/150, 711/151, 711/152, 711/167, 712/10, 712/14, 712/16
• US Class Current: 711/130
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.

Claims

1. A method for reducing the latency of inter-reference ordering in a multiprocessor system having at least one processor module with at least first and second processors sharing a cache, the method comprising the steps of:

issuing a first memory reference operation to the system from the first processor for a data item in response to a cache miss at the shared cache;

providing the data item to the shared cache in response to the issued first memory reference operation;

generating a cache hit at the shared cache in response to a cache access for the data item by the second processor; and

at the second processor, selectively inheriting a commit-signal generated by control logic of the multiprocessor system in response to the issued first memory reference operation to maintain the reduced inter-reference ordering in the system.

2. A method for reducing the latency of inter-reference ordering in a multiprocessor system having at least one processor module with a multi-threaded processor having first and second threads of instructions sharing a cache, the method comprising the steps of:

issuing a first memory reference operation to the system from the first thread for a data item in response to a cache miss at the shared cache;

providing the data item to the shared cache in response to the issued first memory reference operation;

generating a cache hit at the shared cache in response to a cache access for the data item by the second thread; and

at the second thread, selectively inheriting a commit-signal generated by control logic of the multiprocessor system in response to the issued first memory reference operation to maintain the reduced inter-reference ordering in the system.

3. A method for reducing the latency of inter-reference ordering of memory reference operations issued by a first processor to a multiprocessor system having a shared memory, the first processor sharing a cache with at least a second processor, the method comprising the steps of:

issuing a first memory reference operation for a data item to the system in response to a cache miss access to the shared cache for the data item by the first processor, the first memory reference operation requesting the data item from the system;

generating a commit-signal in control logic of the system in response to the first memory reference operation, the commit-signal indicating apparent completion of the first memory reference operation;

providing the data item to the shared cache from the system in response to the first memory reference operation;

generating a cache hit access on the cache to the data item in response to execution of a second memory reference operation by the second processor; and

inheriting, at the second processor, the commit-signal for the first memory reference operation issued by the first processor such that the second processor is inhibited from executing a third memory reference until return of the commit-signal.

4. The method of claim 3 further comprising the step of employing a miss address table (MAT) comprising a plurality of entries, each entry associated with an outstanding memory reference operation to the shared cache, each entry comprising a ComSig flag indicating whether the commit-signal for the outstanding memory reference operation has returned to the MAT.

5. The method of claim 4 wherein the step of employing the MAT comprises the steps of allocating an entry of the MAT in response to the cache miss access.

6. The method of claim 5 wherein the step of employing the MAT further comprises the steps of:

indexing into the MAT to determine if the entry is allocated;

if the entry is allocated, examining the Comsig flag to determine if the commit-signal for the outstanding memory reference operation has returned; and

if the commit-signal has not returned, inheriting the commit-signal of the outstanding memory reference operation.

7. The method of claim 6 further comprising the steps of:

providing a first counter for the first processor and a second counter for the second processor;

incrementing the first counter in response to the step of issuing the outstanding memory reference operation for the data item by the first processor;

incrementing the second counter in response to the step of generating a cache hit access for the data item by the second processor;

returning the commit-signal for the outstanding memory reference operation to the MAT; and

decrementing the first and second counters in response to the step of returning the commit-signal.

8. Apparatus for reducing the latency of inter-reference ordering of memory reference operations in a multiprocessor system having a shared memory, the system including a first processor sharing a cache with at least a second processor, the first processor issuing a first memory reference operation for a data item to the system in response to a cache miss access to the shared cache for the data item, the apparatus comprising:

an ordering point of the system configured to generate a commit-signal in response to the issued first memory reference operation;

means for providing the data item to the shared cache in response to the issued first memory reference operation; and

means for inheriting the commit-signal for the issued first memory reference operation at the second processor in response to a cache hit access to the shared cache for the data item to thereby maintain the reduced inter-reference ordering in the system.

9. The apparatus of claim 8 further comprising a cache controller coupled to the shared cache.

10. The apparatus of claim 9 further comprising a first counter coupled to the cache controller and associated with the first processor.

11. The apparatus of claim 10 further comprising means for incrementing the first counter in response to the issued first memory reference operation.

12. The apparatus of claim 11 further comprising a second counter coupled to the cache controller and associated with the second processor.

13. The apparatus of claim 12 further comprising a miss address table (MAT) coupled to the cache controller, the MAT comprising a plurality of entries, each entry associated with an outstanding memory reference operation to the shared cache.

14. The apparatus of claim 13 wherein each entry of the MAT further comprises a ComSig flag indicating whether a commit-signal for the outstanding memory reference operation has returned to the MAT.

15. The apparatus of claim 14 wherein each entry of the MAT further comprises a ComSig report vector having a plurality of bits, a first report vector bit associated with the first processor sharing the cache and a second report vector bit associated with the second processor sharing the cache.

16. The apparatus of claim 15 wherein the means for inheriting comprises means for incrementing the second counter in response to a cache hit access to the shared cache for the data item by the second processor if the commit-signal has yet to return to the MAT.

17. The apparatus of claim 16 wherein the means for inheriting further comprises means for decrementing the second counter in response to the return of the commit-signal if the second report vector bit is asserted.