Circuits, system, and methods for processing multiple data streams
First Claim
Patent Images
1. An audio stream processor comprising:
- a register file for storing information;
an arithmetic logic unit receiving input information from selected registers in said register file and outputing results to selected registers in said register file;
a parameter address generator for retrieving parameters and coefficients from parameter memory, said parameter address generator operable to exchange information with said register file;
a sample address generator for controlling the exchange of audio sample data with sample memory, said sample address generator operable in response to information received from said parameter memory; and
a dual multiply-accumulate unit for operating on first and second channels of sample data received from said sample address generator unit and information received from selected registers in said register file.
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Abstract
An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.
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Citations
30 Claims
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1. An audio stream processor comprising:
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a register file for storing information; an arithmetic logic unit receiving input information from selected registers in said register file and outputing results to selected registers in said register file; a parameter address generator for retrieving parameters and coefficients from parameter memory, said parameter address generator operable to exchange information with said register file; a sample address generator for controlling the exchange of audio sample data with sample memory, said sample address generator operable in response to information received from said parameter memory; and a dual multiply-accumulate unit for operating on first and second channels of sample data received from said sample address generator unit and information received from selected registers in said register file. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An audio information processing subsystem fabricated on a single-integrated circuit chip comprising:
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a stream processor for simultaneously processing multiple streams of audio data; a program memory coupled to said stream processor by a first bus for storing instructions for controlling said processing subsystem; data memory coupled to said stream processor by a second bus; and direct memory access circuitry for controlling direct memory accesses to a selected one of said program and data memories, said direct memory access circuitry defining a plurality of buffers in said data memory, each buffer associated with one of said data streams. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A multiply-accumulate unit comprising:
a multiply-accumulate path for processing a channel of audio data comprising; first input circuitry for selectively receiving an M-bit wide coefficient word; second input circuitry for selectively receiving an N-bit wide data word; an M-bit by N-bit two'"'"'s complement multiplier array receiving data and coefficients from said input circuitry and outputting a sum vector and a carry vector in response; a P-bit wide carry-save adder for adding said sum and carry vectors and an accumulator output; a P-bit wide adder for adding first and second outputs of said carry-save adder; at lest one P-bit wide accumulator for storing data output from said adder; and circuitry for selectively feeding-back data from said at least one accumulator to said carry-save adder. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. A stream processing system comprising:
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a PCI bus; a host processing subsystem coupled to said PCI bus including; a central processing unit; a host memory; and circuitry for interfacing said central processing unit and said host memory with said PCI bus; and a stream processing subsystem coupled to said PCI bus including; a stream processor for processing a plurality of streams of data simultaneously received, said stream processor including a direct memory access engine operable to exchange information with said host system using direct memory accesses, said direct memory access circuitry controlling a plurality of buffers in memory, each said buffer associated with a corresponding one of said streams of data; and circuitry for interfacing said stream processor with a source of multiple streams of data. - View Dependent Claims (30)
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Specification