Processor test port with scan chains and data streaming
First Claim
1. A method for debugging a processor within a data processing system, the processor having a test port for transferring data into the processor, comprising the steps of:
- inhibiting fetching of instructions into an instruction register of the processor;
loading at least a first debug instruction into the instruction register of the processor;
transferring a stream of data into a first register element within the processor via the test port;
detecting when a first portion of the stream of data is present in the first register element;
moving the first portion of the stream data from the first register element to a first memory accessible to the processor by executing the first debug instruction in the instruction register after the step detecting the first portion;
detecting when a second portion of the stream of data is present in the first register element;
moving the second portion of the stream data from the first register element to a second memory location accessible to the processor by executing the same first debug instruction in the instruction register after the step detecting the second portion; and
repeating the steps of detecting and moving while the step of transferring continues until the entire stream of data is moved to a plurality of memory locations.
1 Assignment
0 Petitions
Accused Products
Abstract
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
119 Citations
20 Claims
-
1. A method for debugging a processor within a data processing system, the processor having a test port for transferring data into the processor, comprising the steps of:
-
inhibiting fetching of instructions into an instruction register of the processor; loading at least a first debug instruction into the instruction register of the processor; transferring a stream of data into a first register element within the processor via the test port; detecting when a first portion of the stream of data is present in the first register element; moving the first portion of the stream data from the first register element to a first memory accessible to the processor by executing the first debug instruction in the instruction register after the step detecting the first portion; detecting when a second portion of the stream of data is present in the first register element; moving the second portion of the stream data from the first register element to a second memory location accessible to the processor by executing the same first debug instruction in the instruction register after the step detecting the second portion; and repeating the steps of detecting and moving while the step of transferring continues until the entire stream of data is moved to a plurality of memory locations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method for debugging a processor within a data processing system, the processor having a test port for transferring a stream of data from the processor, comprising the steps of:
-
inhibiting fetching of instructions into an instruction register of the processor; loading at least a first debug instruction into the instruction register of the processor; moving a first portion of a stream data from a first memory location accessible to the processor to a first register element by executing the first debug instruction in the instruction register; transferring a stream of data from the first register element within the processor via the test port to an external test system; detecting when the first portion of the stream of data is transferred from the first register element; moving a second portion of a stream data from a second memory location accessible to the processor to the first register element by executing the same first debug instruction in the instruction register in response to the step of detecting the transfer of the first portion; and repeating the steps of detecting and moving while the step of transferring continues until the entire stream of data is moved from a plurality of memory locations.
-
-
14. A digital system having a processor, the processor comprising:
-
an instruction register for holding an instruction to be executed; an instruction execution pipeline connected to the instruction register to execute instructions; memory circuitry connected to the processor for holding data and instructions; emulation circuitry connected to the instruction register and to the instruction execution pipeline; a test port connected to the emulation circuitry for transferring a stream of data into or out of the processor; wherein the emulation circuitry comprises; streaming circuitry operable to be accessed by an instruction executed in the instruction pipeline and further operable to transfer the stream of data to and from the test port; detection circuitry operable to detect when a first portion of the stream of data is present in the streaming circuitry; and control circuitry operable to inhibit fetching of instructions into the instruction register of the processor and to load at least a first debug instruction into the instruction register of the processor, further operable to cause the instruction execution pipeline to execute the first debug instruction in response to the detection circuitry detecting the first portion of data and to repeatedly cause the same first instruction to be executed in response to detecting additional portions of the stream of data being present in the streaming circuitry. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification