System configuration and methods for on-the-fly testing of integrated circuits

• US 6,055,661 A
• Filed: 01/18/1996
• Issued: 04/25/2000
• Est. Priority Date: 06/13/1994
• Status: Expired due to Fees

• Current Assignee: Advanced Silicon Test Technology, Inc.
• Original Assignee: Fong Luk
• Inventors: Luk, Fong
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US08/591,225
• Time in Patent Office: 1,559 Days
• Field of Search: 714/736, 714/739, 714/724, 371/25.1, 371/27.2
• US Class Current: 714/736
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

An integrated circuit (IC) testing system is provided by the present invention. The IC testing system is for testing a device under test (DUT) IC. The IC testing system includes an interface to a target system. The target system incorporates a known good IC (KGIC) which is identical to the DUT. The KGIC is implemented on the target system as it is designed to be used during the normal operation of the target system. The target system will then exercise the KGIC by running the diagnostic programs or by sending appropriate instructions or commands to invoke the KGIC to perform different functions for the target system. The interface system provided by the present invention for performing an IC test will then capture the signals to and from the KGIC on-the-fly. The testing system of the present invention will redirect the KGIC input signals to the DUT as testing input signals, i.e., input stimuli. The output signals generated by the will be used as the reference signals for comparison with the corresponding response signals from the DUT for fault detection.

Claims

1. An on-the-fly integrated circuit (IC) testing system for testing a device under test (DUT) IC by employing a known-good IC (KGIC), said IC testing system comprising:

a target system incorporating said known-good IC (KGIC) therein wherein said target system engaging said KGIC as an integrated part of said target system for executing a testing program for directly generating a plurality of spontaneous target system generated input signals to said KGIC and as a result of executing said testing program said KGIC further generating a plurality of spontaneous known-good output signals in response to said spontaneous target system generated input signals;

an input signal transmitting means for transmitting said spontaneous target system generated input signals which are inputted to said KGIC as spontaneous target system generated test stimuli to said DUT IC for generating a plurality of spontaneous test output signals; and

an output signal processing means for receiving and processing said spontaneous known-good output signals and said spontaneous test output signals for determining testing results therefrom whereby said DUT IC is tested with said spontaneous target system generated test stimuli without being limited by a finite number of priorly planned and generated test patterns as test stimuli.

2. The IC testing system of claim 1 further comprises:

a control means for controlling the timing of said spontaneous target system generated test stimuli, said spontaneous known-good output signals, and said spontaneous test output signals.

3. The IC testing system of claim 1 wherein:

said output signal processing means further includes an output signal synchronizing means for synchronizing said test output signals with said known-good output signals.

4. The IC testing system of claim 3 wherein:

said input data transmitting means further includes a transmitting-time control means for controlling the timing of transmitting said spontaneous target system generated test stimuli from said target system to said DUT IC.

5. An on-the-fly integrated circuit (IC) testing system for testing a device under test (DUT) IC by employing a known-good IC (KGIC) identical to said DUT, said testing system comprising:

a target system incorporating said known-good IC (KGIC) therein wherein said target system engaging said KGIC as an integrated part of said taret system for executing a diagnostic program thereon for directly generating a plurality of spontaneous target system generated diagnostic input signals to said KGIC wherein said KGIC further generating a plurality of spontaneous known-good diagnostic output signals in response to said spontaneous target system generated diagnostic input signals;

an input signal transmitting means for transmitting said spontaneous target system generated diagnostic input signals as spontaneous target system generated diagnostic test stimuli to said DUT IC for generating a plurality of spontaneous test output signals; and

an output signal processing means for receiving and processing said spontaneous known-good diagnostic output signals and said spontaneous test output signals for determining testing results therefrom whereby said DUT IC is tested with said spontaneous target system generated diagnostic stimuli without being limited by a finite number of priorly planned and generated test patterns as diagnostic test stimuli.

6. The IC testing system of claim 5 wherein:

said target system is an electronic system and said known-good IC and said DUT IC are ICs which are targeted to be engaged by said electronic system for executing said diagnostic program with said KGIC included as part of an integrated target system.

7. The IC testing system of claim 6 wherein:

said diagnostic program executed on said target system is employed for performing a plurality of real time on-the-fly diagnostic tests on said DUT IC by applying said spontaneous target system generated diagnostic input signals.

8. An on-the-fly testing system for testing a device under test (DUT) by employing a known-good-device (KGD) identical to said DUT, said testing system comprising:

a target system incorporating said KGD therein wherein said target system engaging said KGD as an integrated part of said target system for executing a testing sequence for directly generating a plurality of spontaneous target system generated input signals to said KGD wherein said KGD further generating a plurality of spontaneous known-good output signals in response to said spontaneous target system generated input signals;

an input signal transmitting means for transmitting said plurality of spontaneous target system generated input signals which are inputted to said KGD as spontaneous target system generated test stimuli signals to said DUT for generating a plurality of spontaneous test output signals; and

an output signal processing means for receiving and processing said spontaneous known-good output signals and said spontaneous test output signals for determining testing results therefrom whereby said DUT is tested with said spontaneous target system generated test stimuli without being limited by a finite number of priorly planned and generated test patterns as test stimuli.

9. The testing system of claim 8 further comprises:

a control means for controlling the timing of said spontaneous target system generated diagnostic test stimuli signals, said spontaneous known-good output signals, and said spontaneous test output signals.

10. A method for performing an on-the-fly test for a device-under-test (DUT) integrated circuit (IC) comprising the steps of:

(a) incorporating a known-good IC (KGIC), identical to said DUT IC, in a targe system and engaging said KGIC as an integrated part of said taret system for executing a program thereon for generating and inputting a plurality of spontaneous target system generated input signals to said KGIC and generating a plurality of known-good spontaneous output signals in response to said spontaneous target system generated input signals;

(b) transmitting said spontaneous target system generated input signals generated by said target system from executing said program as spontaneous target system generated test stimuli for inputting to said DUT IC for generating a plurality of spontaneous test output signals; and

(c) receiving and processing said known-good spontaneous output signals and said spontaneous test output signals for determining test results therefrom whereby said DUT IC is tested with said spontaneous target system generated test stimuli without being limited by a finite number of priorly planned and generated test patterns as test stimuli.

11. An integrated circuit (IC) test-stimuli generation system comprising:

a target system incorporating a known-good IC (KGIC) for engaging said KGIC as an integrated part of said target system for executing a testing program for directly generating a plurality of target system generated input signals for inputting to said KGIC; and

a test-stimuli signal transmitting means electrically communicated with said KGIC for extracting said target system generated input signals for inputting said KGIC as a plurality of spontaneous IC testing stimuli signals.

12. The spontaneous IC testing-signal generation system of claim 11 further comprising:

a test verification signal transmitting means electrically communicated with said KGIC for extracting a plurality of KGIC output signals generated in response to said spontaneous target system generated input signals inputted to said KGIC whereby said KGIC output signals are available for test verification.