Method for making bonded metal back-plane substrates

• US 6,057,212 A
• Filed: 05/04/1998
• Issued: 05/02/2000
• Est. Priority Date: 05/04/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: D'Emic, Christopher Peter, Tiwari, Sandip, Jones, Erin Catherine, Chan, Kevin Kok, Solomon, Paul Michael
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US09/072,294
• Time in Patent Office: 729 Days
• Field of Search: 438/455, 438/456, 438/457
• US Class Current: 438/455
• CPC Class Codes: H01L 21/76251 using bonding techniques

Abstract

A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafers to form a bond between the first and second wafers, and detaching a portion of the first wafer from the second wafer. Thus, a device, such as a back-plane for a semiconductor device, formed by the method includes an oxidized substrate, a metal film formed on the oxidized substrate forming a back-gate, a back-gate oxide formed on the back-gate, and a silicon layer formed on the back-gate oxide.

Claims

1. A method of forming a semiconductor structure, comprising steps of:

growing an oxide layer on a substrate to form a first wafer;

separately forming a metal film on an oxidized substrate to form a second wafer;

attaching said first and second wafers;

performing a heat cycle for said first and second wafers to form a bond between said first and second wafers; and

detaching a portion of said first wafer from said second wafer.

2. The method according to claim 1, wherein said substrate comprises a silicon-on-insulator (SOI) substrate, said method further comprising:

aligning said first and second wafers with respect to one another prior to said attaching step; and

dipping said first and second wafers in an acid mixture, and rinsing and drying said first and second wafers,

wherein said metal film comprises a refractory metal.

3. The method according to claim 2, wherein said refractory metal comprises at least one of tungsten, tungsten nitride and titanium nitride.

4. The method according to claim 3, said method further comprising:

after said detaching step, etching any silicon remaining on the second wafer, and removing an oxide therefrom; and

polishing the wafer structure,

wherein said substrate has a surface roughness maintained substantially to less than about 0.5 nm in rms roughness, and wherein said metal film has a surface roughness of substantially less than about 0.5 nm roughness.

5. The method according to claim 3, further comprising a step of particle-cleaning said first and second wafers prior to said dipping step.

6. The method according to claim 3, wherein said dipping step comprises dipping said first and second wafers in approximately 100:

1 diluted hydrofluoric acid mixture.

7. The method according to claim 3, wherein said aligning step comprises using a bonding jig, for orientation alignment and for initiating the attachment of the first and second wafers, and

wherein said bonding is initiated in the jig through a controlled deposition of one of the first and second wafers onto the other of said first and second wafers,

said first and second wafers after attachment being transferrable together.

8. The method according to claim 1, wherein said heat cycle comprises steps of:

performing a thermal cycle including an inert purge of a wafer-containing-chamber, followed by introduction of the first and second wafers being attached together, into a furnace tube at substantially 650°

C. where nitrogen flows, stabilizing the temperature for about 15 minutes at substantially 650°

C., and an annealing for approximately 30 minutes, a thirty-minute temperature rise to substantially 750°

C., stabilization for approximately 15 minutes at substantially 750°

C. and an annealing for approximately 30 minutes, followed by similar steps at substantially 850°

C., 950°

C., and 1050°

C., and up to substantially 1100°

C. for up to about 2.5 hours, and subsequently a 90-minute cool-down to substantially 650°

C., thereby to form a substantially stress-free bond between said first and second wafers.

9. The method according to claim 1, wherein said portion of said first wafer comprises a sacrificial wafer which is detachable by grinding.

10. The method according to claim 9, wherein said portion includes an oxidized substrate of said first wafer.

11. The method according to claim 1, wherein said portion includes said substrate of said first wafer.

12. The method according to claim 1, wherein a bonded interface is in a buried oxide of said oxidized substrate.

13. The method according to claim 1, wherein said step of performing a heat cycle includes performing said heat cycle in a nitrogen ambient.

14. The method according to claim 1, further comprising a step of hydrogen-treating at least one of a surface of said first wafer and a surface of said second wafer prior to said aligning step.

15. A method of forming a back-plane for a semiconductor device, comprising steps of:

growing an oxide layer on a first substrate to form a first wafer;

separately forming a metal film on an oxidized second substrate to form a second wafer;

dipping said first and second wafers in an acid mixture;

aligning said first and second wafers with respect to one another for attachment;

performing a heat cycle to form a bond between said first and second wafers; and

detaching a portion of the first wafer from the second wafer, to form a wafer structure.

16. The method according to claim 15, further comprising steps of:

after said dipping step, rinsing and drying said first and second wafers;

after said detaching step, etching silicon remaining on a surface of the wafer structure, and removing oxide therefrom; and

polishing the wafer structure,

wherein said metal film comprises a refractory metal.

17. The method according to claim 15, wherein said metal film comprises at least one of tungsten, tungsten nitride, titanium nitride, and alloys thereof.

18. The method according to claim 15, wherein said step of performing a heat cycle includes performing said heat cycle in a nitrogen ambient.

19. The method according to claim 15, wherein said substrate has a surface roughness maintained substantially to less than about 0.5 nm in rms roughness, and wherein said metal film has a roughness of substantially less than about 0.5 nm roughness.

20. The method according to claim 15, further comprising a step of particle-cleaning said first and second wafers prior to said dipping step.

21. The method according to claim 15, wherein said dipping step comprises dipping said first and second wafers in approximately 100:

1 diluted hydrofluoric acid mixture.

22. The method according to claim 15, wherein said aligning step comprises using a bonding jig, which allows for orientation alignment, to initiate the attachment of the first and second wafers, and

wherein said bonding is initiated in the jig through a controlled deposition of one of the first and second wafers onto the other of said first and second wafers,

said first and second wafers being transferrable together.

23. The method according to claim 15, wherein said heat cycle comprises steps of:

performing a thermal cycle including a nitrogen purge of a wafer-containing-chamber so that gas flows, thereby to purge the chamber, followed by introduction of the first and second wafers attached together, into a furnace tube at substantially 650°

C. where nitrogen flows, stabilizing the temperature for about 15 minutes at substantially 650°

C., and an annealing for approximately 30 minutes, an approximate thirty-minute rise to substantially 750°

C., stabilization for approximately 15 minutes at substantially 750°

C. and an annealing for approximately 30 minutes, followed by similar steps at substantially 850°

C., 950°

C., and 1050°

C., and up to substantially 1100°

C. for up to 2.5 hours, and subsequently a 90-minute cool-down to substantially 650°

C., thereby to form a substantially stress-free bond.

24. The method according to claim 16, wherein the first wafer comprises a sacrificial wafer which is detachable by grinding.

25. The method according to claim 16, wherein said oxidized silicon substrate includes a buried oxide layer including a bonded interface between said first wafer and said second wafer.

26. A method of forming a back-plane for a semiconductor device, comprising steps of:

forming a first wafer including a silicon-on-insulator (SOI) structure;

bonding said first wafer to a second wafer, said second wafer including a refractory metal-coated substrate; and

removing a portion of said first wafer from said second wafer, thereby forming the backplane.