High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

• US 6,057,555 A
• Filed: 10/26/1998
• Issued: 05/02/2000
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): Wojciechowicz, Edward
• Application Number:
  US09/179,258
• Time in Patent Office: 554 Days
• Field of Search: 257/213, 257/280, 257/327, 257/347, 257/350, 257/369
• US Class Current: 257/9
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Claims

1. A transistor comprising:

an electrically insulating substrate having a first surface; and

a layer of silicon formed on said first surface of said electrically insulating substrate, wherein;

said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 achieved by performing any processing of said silicon layer which subjects the silicon layer to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment; and

said layer of silicon has a thickness which is less than approximately 270 nm.

2. A transistor as defined in claim 1 wherein said transistor further comprises a field-effect-transistor (FET).

3. A transistor as defined in claim 1 wherein said electrically insulating substrate further comprises sapphire.

4. A MOSFET comprising:

a sapphire substrate; and

a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 achieved by performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment, wherein said layer of silicon further comprises;

a source region;

a drain region; and

a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 thereby capable of being fully depleted.

5. A MOSFET as defined in claim 4 wherein said source region further comprises dopant atoms.

6. A MOSFET as defined in claim 4 wherein said drain region further comprises dopant atoms.

7. A MOSFET as defined in claim 4 wherein said channel region further comprises dopant atoms in a concentration which has a lower limit which is sufficient to induce surface channel conduction and an upper limit which does not prevent full depletion of said channel region.

8. A MOSFET as defined in claim 4 further comprising a gate dielectric layer adjacent said channel region and a gate conductor layer adjacent said gate dielectric layer.

9. A MOSFET as defined in claim 8 wherein said gate conductor layer further comprises N⁺ polysilicon in contact with said gate dielectric layer.

10. A MOSFET as defined in claim 8 wherein said gate conductor layer further comprises P⁺ polysilicon in contact with said gate dielectric layer.

11. A MOSFET as defined in claim 8 wherein said gate conductor layer further comprises a material having a metal work function which is in the range of from 4.5 eV to 4.7 eV.

12. A MOSFET as defined in claim 11 wherein said material having a metal work function which is in the range of from 4.5 eV to 4.7 eV is selected from a group of materials which includes P⁺ polygermanium, tungsten, chromium, indium tin oxide and titanium nitride.

13. A MOSFET as defined in claim 8 further comprising a sidewall spacer adjacent said gate dielectric layer and adjacent said gate conductor layer.

14. A MOSFET as defined in claim 4 wherein said source region further comprises a lightly doped source region.

15. A MOSFET as defined in claim 4 wherein said drain region further comprises a lightly doped drain region.

16. A MOSFET as defined in claim 4 wherein said channel region is intentionally doped to adjust threshold voltage.

17. A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2, said transistor produced by the process comprising the steps of;

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and

performing all processing of said layer of silicon subsequent to said ion implanting step which subject said layer of silicon to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment, thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×

10¹¹ cm^-2.

18. A transistor produced by the process defined in claim 17 further comprising the step of:

maintaining said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said layer of silicon during said ion implanting step.

19. A transistor produced by the process defined in claim 18 wherein said predetermined temperature of said layer of silicon during formation of said buried amorphous region is maintained at approximately zero degrees centigrade (0°

C.).

20. A transistor produced by the process defined in claim 17 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

21. A transistor produced by the process defined in claim 17 wherein said transistor is a MOSFET.

22. A transistor comprising:

an electrically insulating substrate having a first surface; and

a layer of silicon formed on said first surface of said electrically insulating substrate, wherein said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 achieved by adhering to the following processing criteria;

1) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment; and

2) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950°

C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

23. A transistor as defined in claim 22 wherein said transistor further comprises a field-effect-transistor (FET).

24. A transistor as defined in claim 22 wherein said electrically insulating substrate further comprises sapphire.

25. A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2,said transistor produced by the process comprising the steps of;

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

selecting an areal portion of said layer of silicon and maintaining said areal portion of said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said areal portion of said layer of silicon during said ion implanting step;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed;

performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment; and

performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950°

C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

26. A MOSFET comprising:

a sapphire substrate; and

a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 achieved by adhering to the following processing criteria;

1) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment; and

2) performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950°

C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment, wherein said layer of silicon further comprises;

a source region;

a drain region; and

a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 thereby capable of being fully depleted.

27. A MOSFET as defined in claim 26 wherein said source region further comprises dopant atoms.

28. A MOSFET as defined in claim 26 wherein said drain region further comprises dopant atoms.

29. A MOSFET as defined in claim 26 wherein said channel region further comprises dopant atoms in a concentration which has a lower limit which is sufficient to induce surface channel conduction and an upper limit which does not prevent full depletion of said channel region.

30. A MOSFET as defined in claim 26 further comprising a gate dielectric layer adjacent said channel region and a gate conductor layer adjacent said gate dielectric layer.

31. A MOSFET as defined in claim 30 wherein said gate conductor layer further comprises N⁺ polysilicon in contact with said gate dielectric layer.

32. A MOSFET as defined in claim 30 wherein said gate conductor layer further comprises P⁺ polysilicon in contact with said gate dielectric layer.

33. A MOSFET as defined in claim 30 wherein said gate conductor layer further comprises a material having a metal work function which is in the range of from 4.5 eV to 4.7 eV.

34. A MOSFET as defined in claim 33 wherein said material having a metal work function which is in the range of from 4.5 eV to 4.7 eV is selected from a group of materials which includes P⁺ polygermanium, tungsten, chromium, indium tin oxide and titanium nitride.

35. A MOSFET as defined in claim 30 further comprising a sidewall spacer adjacent said gate dielectric layer and adjacent said gate conductor layer.

36. A MOSFET as defined in claim 26 wherein said source region further comprises a lightly doped source region.

37. A MOSFET as defined in claim 26 wherein said drain region further comprises a lightly doped drain region.

38. A MOSFET as defined in claim 26 wherein said channel region is intentionally doped to adjust threshold voltage.

39. A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2, said transistor produced by the process comprising the steps of;

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed;

performing any processing of said layer of silicon which subjects said layer of silicon to temperatures in excess of approximately 950°

C. in an oxidizing ambient environment; and

performing any processing of said layer of silicon which subjects said layer of silicon to temperatures which are less than approximately 950°

C. in either one of an oxidizing ambient environment or a non-oxidizing ambient environment.

40. A transistor produced by the process defined in claim 39 further comprising the step of:

maintaining said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said layer of silicon during said ion implanting step.

41. A transistor produced by the process defined in claim 40 wherein said predetermined temperature of said layer of silicon during formation of said buried amorphous region is maintained at approximately zero degrees centigrade (0°

C.).

42. A transistor produced by the process defined in claim 39 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

43. A transistor produced by the process defined in claim 39 wherein said transistor is a MOSFET.

44. A transistor comprising:

an electrically insulating substrate having a first surface; and

a layer of silicon formed on said first surface of said electrically insulating substrate, wherein;

said layer of silicon has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 achieved by performing any processing of said silicon layer which exposes said silicon layer to a non-oxidizing ambient environment at temperatures of less than or equal to approximately 950°

C.; and

said layer of silicon has a thickness which is less than approximately 270 nm.

45. A transistor as defined in claim 44 wherein said transistor further comprises a field-effect-transistor (FET).

46. A transistor as defined in claim 44 wherein said electrically insulating substrate further comprises sapphire.

47. A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2, said transistor produced by the process comprising the steps of;

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

selecting an areal portion of said layer of silicon and maintaining said areal portion of said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said areal portion of said layer of silicon during said ion implanting step;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and

performing all annealing and/or processing procedures which expose said layer of silicon to a non-oxidizing ambient environment at or below a temperature of approximately 950°

C., thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×

10¹¹ cm^-2.

48. A MOSFET comprising:

a sapphire substrate; and

a layer of silicon deposited on said sapphire substrate, said layer of silicon having an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 achieved by performing any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment at temperatures of less than or equal to approximately 950°

C., wherein said layer of silicon further comprises;

a source region;

a drain region; and

a channel region, wherein said channel region is less than approximately 270 nm thick and has an areal density of electrically active states in regions which are not intentionally doped which is less than approximately 5×

10¹¹ cm^-2 thereby capable of being fully depleted.

49. A MOSFET as defined in claim 48 wherein said source region further comprises dopant atoms.

50. A MOSFET as defined in claim 48 wherein said drain region further comprises dopant atoms.

51. A MOSFET as defined in claim 48 wherein said channel region further comprises dopant atoms in a concentration which has a lower limit which is sufficient to induce surface channel conduction and an upper limit which does not prevent full depletion of said channel region.

52. A MOSFET as defined in claim 48 further comprising a gate dielectric layer adjacent said channel region and a gate conductor layer adjacent said gate dielectric layer.

53. A MOSFET as defined in claim 52 wherein said gate conductor layer further comprises N⁺ polysilicon in contact with said gate dielectric layer.

54. A MOSFET as defined in claim 52 wherein said gate conductor layer further comprises P⁺ polysilicon in contact with said gate dielectric layer.

55. A MOSFET as defined in claim 52 wherein said gate conductor layer further comprises a material having a metal work function which is in the range of from 4.5 eV to 4.7 eV.

56. A MOSFET as defined in claim 55 wherein said material having a metal work function which is in the range of from 4.5 eV to 4.7 eV is selected from a group of materials which includes P⁺ polygermanium, tungsten, chromium, indium tin oxide and titanium nitride.

57. A MOSFET as defined in claim 52 further comprising a sidewall spacer adjacent said gate dielectric layer and adjacent said gate conductor layer.

58. A MOSFET as defined in claim 48 wherein said source region further comprises a lightly doped source region.

59. A MOSFET as defined in claim 48 wherein said drain region further comprises a lightly doped drain region.

60. A MOSFET as defined in claim 48 wherein said channel region is intentionally doped to adjust threshold voltage.

61. A transistor formed in a silicon layer which is formed on a sapphire substrate wherein said silicon layer is less than approximately 270 nm thick and has an areal density of electrically active states in regions not intentionally doped which is less than approximately 5×

10¹¹ cm^-2, said transistor produced by the process comprising the steps of;

epitaxially depositing a layer of silicon on a surface of a sapphire substrate;

implanting a given ion species into said layer of silicon under such conditions that said implanted ions form a buried amorphous region in said silicon layer which extends substantially from said surface of said sapphire substrate into said layer of silicon, thus leaving a surface layer of monocrystalline silicon covering said buried amorphous region;

annealing the wafer to induce solid phase epitaxial regrowth of said buried amorphous region using said surface layer of monocrystalline silicon as a crystallization seed; and

performing all annealing and/or processing procedures which expose said layer of silicon to a non-oxidizing ambient environment at or below a temperature of approximately 950°

C., thereby maintaining an areal density of electrically active states in regions of the silicon not intentionally doped which is less than approximately 5×

10¹¹ cm^-2.

62. A transistor produced by the process defined in claim 61 further comprising the step of:

maintaining said layer of silicon during formation of said buried amorphous region at or below a predetermined temperature which is substantially uniform throughout said layer of silicon during said ion implanting step.

63. A transistor produced by the process defined in claim 62 wherein said predetermined temperature of said layer of silicon during formation of said buried amorphous region is maintained at approximately zero degrees centigrade (0°

C.).

64. A transistor produced by the process defined in claim 61 further comprising the step of forming a channel region in said layer of silicon which is intentionally doped to adjust a threshold voltage of said transistor.

65. A transistor produced by the process defined in claim 61 wherein said transistor is a MOSFET.