Silicon carbide semiconductor device and manufacturing method thereof

• US 6,057,558 A
• Filed: 03/04/1998
• Issued: 05/02/2000
• Est. Priority Date: 03/05/1997
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Hara, Kunihiko, Kumar, Rajesh, Yamamoto, Tsuyoshi, Takeuchi, Yuichi, Hara, Kazukuni, Naito, Masami
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Wille, Douglas A.
• Application Number:
  US09/034,344
• Time in Patent Office: 790 Days
• Field of Search: 257/77
• US Class Current: 257/77
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n^- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.

Claims

1. A silicon carbide semiconductor device comprising:

a semiconductor substrate made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer;

a second semiconductor layer of the first conductive type consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate insulating film formed at least on a surface of the second semiconductor layer;

a gate electrode layer formed on the gate insulating film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate,

wherein when a reverse bias voltage is impressed on a pn junction between the first electrode layer and the second electrode layer a pn junction between the high-resistance semiconductor layer and the first semiconductor layer undergoes avalanche breakdown before the second semiconductor layer between the high-resistance semiconductor layer and the semiconductor region suffers punch-through.

2. A silicon carbide semiconductor device comprising:

a semiconductor substrate made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer;

a second semiconductor layer of the first conductive type consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate insulating film formed at least on a surface of the second semiconductor layer;

a gate electrode layer of the second conductive type formed on the gate insulating film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate,

wherein a film thickness X(μ

m) and an impurity concentration N(cm^-3) of the second semiconductor layer with respect to a withstand voltage Y(V) thereof satisfy the relationship Y<

-10000{(X-0.8)+0.3(logN-15)}.

3. A silicon carbide semiconductor device comprising:

a semiconductor substrate made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer;

a second semiconductor layer of the first conductive type consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate insulating film formed at least on a surface of the second semiconductor layer;

a gate electrode layer of the first conductive type formed on the gate insulating film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate,

wherein a film thickness X(μ

m) and an impurity concentration N(cm^-3) of the second semiconductor layer with respect to a withstand voltage Y(V) thereof satisfy the relationship Y<

-10000{(X-0.6)+0.3(logN-15)}.

4. A silicon carbide semiconductor device comprising:

a semiconductor substrate consisting of hexagonal system monocrystalline silicon carbide and made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer and reaching the high-resistance semiconductor layer and having a side face substantially parallel with a [1100] direction;

a second semiconductor layer consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate insulating film formed at least on a surface of the second semiconductor layer;

a gate electrode layer formed on the gate insulating film in the trench;

a first electrode layer formed at least on a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate.

5. A silicon carbide semiconductor device according to claim 4, wherein a shape of the trench at the surface of the semiconductor substrate is a hexagon having all its internal angles substantially equal.

6. A silicon carbide semiconductor device according to claim 4, wherein the second semiconductor layer is of the first conductive type.

7. A silicon carbide semiconductor device according to claim 5, wherein the second semiconductor layer is of the first conductive type.

8. A silicon carbide semiconductor device according to claim 6, wherein the second semiconductor layer has a film thickness of at least 250 nm and an impurity concentration of not more than 7×

10¹⁵ cm^-3.

9. A silicon carbide semiconductor device according to claim 7, wherein the second semiconductor layer has a film thickness of at least 250 nm and an impurity concentration of not more than 7×

10¹⁵ cm^-3.

10. A silicon carbide semiconductor device comprising:

a semiconductor substrate consisting of silicon carbide and made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer;

a second semiconductor layer consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate oxide film formed at least on a surface of the second semiconductor layer;

a gate electrode layer formed on the gate oxide film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate,

wherein when a reverse bias voltage is impressed on a pn junction between the first electrode layer and the second electrode layer a pn junction between the high-resistance semiconductor layer of the first conductive type and the first semiconductor layer of the second conductive type becomes conductive before a surface of the gate oxide film at a bottom of the trench undergoes avalanche breakdown.

11. A silicon carbide semiconductor device comprising:

a semiconductor substrate consisting of silicon carbide and made up of a first low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type, a second low-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer and reaching at least the second low-resistance semiconductor layer;

a second semiconductor layer consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate oxide film formed at least on a surface of the second semiconductor layer;

a gate electrode layer formed on the gate oxide film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate.

12. A silicon carbide semiconductor device according to claim 11, wherein a film thickness and an impurity concentration of the second low-resistance semiconductor layer are so set that when a reverse bias voltage is impressed on a pn junction between the first electrode layer and the second electrode layer a pn junction between the second low-resistance semiconductor layer and the first semiconductor layer undergoes avalanche breakdown before the surface of the gate oxide film at the bottom of the trench undergoes avalanche breakdown.

13. A silicon carbide semiconductor device comprising:

a semiconductor substrate consisting of silicon carbide and made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer;

a second semiconductor layer consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate oxide film formed at least on a surface of the second semiconductor layer;

a gate electrode layer formed on the gate oxide film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate; and

a second electrode layer formed on a rear side of the semiconductor substrate,

wherein the high-resistance semiconductor layer is set to a thickness such that, when a reverse bias voltage is impressed on a pn junction between the first electrode layer and the second electrode layer and a pn junction between the high-resistance semiconductor layer and the first semiconductor layer has become conductive, a depletion layer extending from the gate oxide film toward the low-resistance semiconductor layer does not reach the low-resistance semiconductor layer.

14. A silicon carbide semiconductor device according to claim 13, wherein the high-resistance semiconductor layer is set to a thickness such that, when the reverse bias voltage is impressed on the pn junction between the first electrode layer and the second electrode layer and an electric field due to the reverse bias voltage has reached a critical electric field strength at which the pn junction between the high-resistance semiconductor layer and the first semiconductor layer undergoes avalanche breakdown, the depletion layer extending from the gate oxide film toward the low-resistance semiconductor layer does not reach the low-resistance semiconductor layer.

15. A silicon carbide semiconductor device comprising:

a semiconductor substrate consisting of silicon carbide and made up of a low-resistance semiconductor layer of a first conductive type, a high-resistance semiconductor layer of the first conductive type and a first semiconductor layer of a second conductive type;

a semiconductor region of the first conductive type formed in a predetermined region of a surface of the first semiconductor layer;

a trench passing from a surface of the semiconductor substrate through the semiconductor region and the first semiconductor layer;

a second semiconductor layer consisting of a thin film of silicon carbide formed at least on a surface of the first semiconductor layer at a side face of the trench;

a gate oxide film formed at least on a surface of the second semiconductor layer;

a gate electrode layer formed on the gate oxide film in the trench;

a first electrode layer formed at least on a surface of a part of the semiconductor region at the surface of the semiconductor substrate;

a second electrode layer formed on a rear side of the semiconductor substrate; and

an embedded semiconductor layer formed in the high-resistance semiconductor layer to be away from the trench and in contact with the first semiconductor layer.

16. A silicon carbide semiconductor device according to claim 15, wherein the embedded semiconductor layer is of the first conductive type.

17. A silicon carbide semiconductor device according to claim 15, wherein the embedded semiconductor layer is of the second conductive type.