Semiconductor integrated circuit device with MOS transistor and MOS capacitor and method for manufacturing the same

• US 6,057,572 A
• Filed: 06/11/1998
• Issued: 05/02/2000
• Est. Priority Date: 06/14/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshida, Kenji, Ito, Yasushi
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/095,593
• Time in Patent Office: 691 Days
• Field of Search: 257/296, 257/532
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A method for fabricating a semiconductor device using an etching stopper film without increasing a number of steps of photoetching and without degrading the device characteristics. A MOS capacitor having a small coefficient of voltage is formed by forming a thick oxide film which is different from a gate oxide film of a MOS transistor to be formed on the same substrate and by implanting impurity of an amount which will not destroy insulation right under the oxide film. At this time, the electrode of the MOS capacitor is formed by the same layer with that of the gate electrode of the MOS transistor to equalize the height of both the electrodes.

Claims

1. A semiconductor integrated circuit device, comprising:

a semiconductor substrate;

a MOS type field effect transistor having a first silicon oxide film formed on said semiconductor substrate as a gate insulating film; and

a capacitor having a second silicon oxide film on said semiconductor substrate as a dielectric film, a first electrode comprising a portion of said semiconductor substrate and a second electrode on said second silicon oxide film;

wherein said second silicon oxide film is thicker than said first silicon oxide film.

2. The semiconductor integrated circuit device according to claim 1, wherein the thickness of said first silicon oxide film is about 2 to 15 nm and the thickness of said second silicon oxide film is about 10 to 45 nm.

3. The semiconductor integrated circuit device according to claim 1, further comprising a device separating region isolating said capacitor from said MOS type field effect transistor.

4. The semiconductor integrated circuit device according to claim 1, wherein said MOS type field effect transistor has a gate electrode on said first silicon oxide film which is formed by the same process as the second electrode of said capacitor.

5. The semiconductor integrated circuit device according to claim 1, further comprising bias dependency control means provided in said semiconductor substrate below said second silicon oxide film.

6. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor integrated circuit device has an analog core including an analog-digital converter.

7. A semiconductor integrated circuit device, comprising:

a semiconductor substrate including a well region of one type of conductivity;

a MOS type field effect transistor having a first silicon oxide film formed on said well region as a gate insulating film;

a capacitor having a second silicon oxide film formed on said semiconductor substrate as a dielectric film, a first electrode comprising a potion of said well region and a second electrode formed on said second silicon oxide film, said second silicon oxide film having a thickness which reduces a voltage dependency of said capacitor and which is thicker than the thickness of said first silicon oxide film; and

a high concentrate impurity diffusing region provided below said second silicon oxide film and having a conductivity type opposite to the one type of conductivity of said well region.

8. The semiconductor integrated circuit device according to claim 7, wherein the thickness of said first silicon oxide film is about 2 to 15 nm and the thickness of said second silicon oxide film is about 10 to 45 nm.

9. The semiconductor integrated circuit device according to claim 7, further comprising a device separating region isolating said capacitor from said MOS type field effect transistor.

10. The semiconductor integrated circuit device according to claim 7, wherein said MOS type field effect transistor has an electrode which is formed by the same process as the second electrode of said capacitor.

11. The semiconductor integrated circuit device according to claim 7, wherein the impurity concentration of said high concentrate impurity diffusing region is within a range from about 1E14 cm^-3 to about 1E20 cm^-3.

12. The semiconductor integrated circuit device according to claim 7, further comprising:

a second electrode connected to a terminal formed in said semiconductor substrate.

13. The semiconductor integrated circuit device according to claim 12, wherein the impurity concentration of said high concentrate contact region is greater than about E20 cm^-3.

14. The semiconductor integrated circuit device according to claim 12, wherein the depth of said high concentrate contact region from the surface of said semiconductor substrate is less than the depth of said high concentrate impurity diffusing region from said semiconductor substrate.

15. The semiconductor integrated circuit device according to claim 12, wherein the impurity concentration of said high concentrate contact region is greater than the impurity concentration of said high concentrate impurity diffusing region.

16. The semiconductor integrated circuit device according to claim 7, wherein said semiconductor integrated circuit device has an analog core including an analog-digital converter.