Face on face flip chip integration

• US 6,057,598 A
• Filed: 01/31/1997
• Issued: 05/02/2000
• Est. Priority Date: 01/31/1997
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Reiter, Herbert, Payne, Robert L.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/794,272
• Time in Patent Office: 1,187 Days
• Field of Search: 257/777, 257/778, 257/737, 257/738, 257/723
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention provides methods and apparatus capable of efficiently combining a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. The logic circuit die is produced independently with a logic circuit fabrication process that optimizes the logic circuit'"'"'s performance and reduces costs, and the memory circuit die, which may contain a large memory circuit, can be produced independently with a memory circuit fabrication process that optimizes the memory circuit'"'"'s performance and reduces costs. The circuit dies are attached directly together in a flip-chip fashion to create a unitary integrated circuit assembly having a high-performance, low impedance, wide-word interface. This integrated circuit assembly can be enclosed within a typical integrated circuit package for insertion on a circuit board, such as those used in personal computers and other common electronic applications.

Claims

1. An integrated circuit device comprising:

an integrated circuit assembly including

(a) a memory circuit die made with a memory circuit fabrication process, said memory circuit die having

(i) a first plurality of conductive contacts arranged on a first connecting side of said memory circuit die; and

(ii) a memory circuit formed on said memory circuit die and electrically coupled to said first plurality of conductive contacts; and

(b) a logic circuit die made with a logic circuit fabrication process, said memory circuit die and said logic circuit die being attached together, said logic circuit die having

(i) a second plurality of conductive contacts arranged on a second connecting side of said logic circuit die; and

(ii) a logic circuit formed on said logic circuit die and electrically coupled to said second plurality of connecting contacts;

wherein said memory circuit die and said logic circuit die are attached together in a flip-chip fashion with said first connecting side in close proximity to said second connecting side and with said first plurality of conductive contacts connected to said second plurality of contacts to provide electrical connections between said memory circuit and said logic circuit, thereby forming a unitary, integrated circuit assembly.

2. The integrated circuit device of claim 1, wherein said first circuit die and said second circuit die are comprised of substrate materials having similar coefficients of thermal expansion such that mechanical stress on said first plurality of contacts and said second plurality of contacts is minimized.

3. The integrated circuit device of claim 1, wherein said memory circuit is a dynamic random access memory.

4. The integrated circuit device of claim 1, wherein said memory circuit is a static random access memory.

5. The integrated circuit device of claim 1, wherein said memory circuit is a flash memory.

6. The integrated circuit device of claim 1 wherein said first connecting side has a greater surface area than said second connecting side.

7. The integrated circuit device of claim 1 wherein said second connecting side has a greater surface area than said first connecting side.

8. The integrated circuit device of claim 1 wherein said first conductive contacts are conductive bumps extending outwardly from said first connecting side.

9. The integrated circuit device of claim 8 wherein said second conductive contacts are pads.

10. The integrated circuit device of claim 1 wherein said second connecting contacts are conductive bumps extending outwardly from said second connecting side.

11. The integrated circuit device of claim 10 wherein said first conductive contacts are pads.

12. The integrated circuit device of claim 1 further comprising:

(a) an insulating package enclosing said integrated circuit assembly; and

(b) a plurality of conductive leads electrically coupled to said integrated circuit assembly and extending from said insulating package.

13. The integrated circuit assembly of claim 1 wherein said second connecting contacts are conductive bumps extending outwardly from said second connecting side.

14. A method for creating an integrated circuit device comprising:

creating an integrated circuit assembly by

providing a memory circuit die made with a memory circuit fabrication process, said memory circuit die having a first plurality of conductive contacts arranged on a first connecting side of said memory circuit die, and a memory circuit formed on said memory circuit die and electrically coupled to said first plurality of conductive contacts;

providing a logic circuit die made with a logic circuit fabrication process, said logic circuit die having a second plurality of conductive contacts arranged on a second connecting side of said logic circuit die, and a logic circuit formed on said logic circuit die and electrically coupled to said second plurality of connecting contacts; and

attaching said memory circuit die and said logic circuit die together in a flip-chip fashion with said first connecting side in close proximity to said second connecting side and with said first plurality of conductive contacts connected to said second plurality of contacts to provide electrical connections between said memory circuit and said logic circuit, thereby forming a unitary, integrated circuit assembly.

15. The method of claim 14 wherein said first circuit die and said second circuit die are comprised of substrate materials having similar coefficients of thermal expansion such that mechanical stress on said first plurality of contacts and said second plurality of contacts is minimized.

16. The method of claim 14, wherein said memory circuit is a dynamic random access memory.

17. The method of claim 14, wherein said memory circuit is a static random access memory.

18. The method of claim 14, wherein said memory circuit is a flash memory.

19. The method of claim 14 wherein said first connecting side has a greater surface area than said second connecting side.

20. The method of claim 14 wherein said second connecting side has a greater surface area than said first connecting side.

21. The method of claim 14 wherein said first conductive contacts are conductive bumps extending outwardly from said first connecting side.

22. The method of claim 21 wherein said second conductive contacts are pads.

23. The method of claim 14 wherein said second connecting contacts are conductive bumps extending outwardly from said second connecting side.

24. The method of claim 23 wherein said first conductive contacts are pads.

25. The method of claim 14 further comprising:

enclosing said integrated circuit assembly within an insulating package; and

providing a plurality of conductive leads electrically coupled to said integrated circuit assembly and extending from said insulating package.

26. An integrate circuit assembly comprising:

a first circuit die made with a first circuit fabrication process, said first circuit die having a first plurality of conductive contacts arranged on a first connecting side of said first circuit die;

a second circuit die made with a second circuit fabrication process, said first circuit die and said second circuit die being attached together, said second circuit die having a second plurality of conductive contacts arranged on a second connecting side of said second circuit die; and

wherein said first circuit die and said second circuit die are attached together in a flip-chip fashion with said first connecting side in close proximity to said second connecting side and with said first plurality of conductive contacts connected to said second plurality of contacts to provide electrical connections between said first circuit die and said second circuit die, thereby forming a unitary, integrated circuit assembly.

27. The integrated circuit assembly of claim 26 wherein said first circuit die and said second circuit die are comprised of substrate materials having similar coefficients of thermal expansion such that mechanical stress on said first plurality of contacts and said second plurality of contacts is minimized.

28. The integrated circuit assembly of claim 26, wherein said first circuit die includes a dynamic random access memory.

29. The integrated circuit assembly of claim 26, wherein said first circuit die includes a static random access memory.

30. The integrated circuit assembly of claim 26, wherein said first circuit die includes a flash memory.

31. The integrated circuit assembly of claim 26, wherein said first circuit die includes an analog circuit.

32. The integrated circuit assembly of claim 26 wherein said first connecting side has a greater surface area than said second connecting side.

33. The integrated circuit assembly of claim 26 wherein said second connecting side has a greater surface area than said first connecting side.

34. The integrated circuit assembly of claim 33 wherein said second conductive contacts are pads.

35. The integrated circuit assembly of claim 26 wherein said first conductive contacts are conductive bumps extending outwardly from said first connecting side.

36. The integrated circuit assembly of claim 35 wherein said first conductive contacts are pads.