Programmable pin designation for semiconductor devices

• US 6,057,705 A
• Filed: 05/28/1998
• Issued: 05/02/2000
• Est. Priority Date: 05/28/1998
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Boles, Brian E., Wojewoda, Igor, Drake, Rodney J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/085,826
• Time in Patent Office: 705 Days
• Field of Search: 326/38, 326/37, 326/39, 326/40
• US Class Current: 326/38
• CPC Class Codes: G06F 1/22 Means for limiting or controlling the pin/gate ratio
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/1731 Optimisation thereof

Abstract

The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programming logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer'"'"'s requirements. The invention is to exist on a single, monolithic semiconductor device.

Claims

1. A system for programmably designating semiconductor device pins comprising, in combination:

a programming port for receiving a plurality of pin designation instructions;

configuration logic coupled to the programming port for storing the plurality of pin designation instructions;

selection logic coupled to the programming port for selecting the function of at least one pin designation;

at least one pin coupled to the selection logic and that is programmably designated to perform one of a plurality of I/O functions;

a plurality of pins with a predesignated address function; and

programming logic coupled to the programming port for interpreting the plurality of pin designation instructions.

2. The system in accordance with claim 1 wherein the programming port, the configuration logic, the selection logic, the at least one pin and the plurality of pins with the predesignated address function are all located on a single, monolithic semiconductor device.

3. The system in accordance with claim 1 wherein the programming logic is comprised of a processing unit that interprets the plurality of pin designation instructions and stores a plurality of pin designation commands within the configuration logic.

4. The system in accordance with claim 3 wherein the plurality of pin designation commands are encoded commands.

5. The system in accordance with claim 1 wherein the selection logic is comprised of at least one multiplexer.

6. The system in accordance with claim 5 wherein the selection logic is further comprised of decoding logic for decoding the plurality of pin designation commands.

7. A method for programmably designating semiconductor pins comprising the steps of:

providing a plurality of pin designation instructions to a programming port;

providing at least one configuration register to store the plurality of pin designation instructions received from the programming port;

providing selection logic that is controlled by the pin designation instructions stored in the at least one configuration register for selecting one of a plurality of I/O functions;

providing at least one pin coupled to the selection logic and that is programmably designated to perform one of the plurality of I/O functions;

providing a plurality of pins with a predesignated address function; and

providing programming logic coupled to the programming port for interpreting the plurality of pin designation instructions.