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Dual purpose apparatus, method and system for accelerated graphics port and fibre channel arbitrated loop interfaces

  • US 6,057,863 A
  • Filed: 10/31/1997
  • Issued: 05/02/2000
  • Est. Priority Date: 10/31/1997
  • Status: Expired due to Fees
First Claim
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1. A computer system having a core logic chipset configurable as either an accelerated graphics port (AGP) interface or a Fibre Channel Arbitrated Loop (FC-AL) interface and connects a computer processor and memory thereto, said system comprising:

  • a central processing unit connected to a host bus;

    a random access memory connected to a random access memory bus;

    a core logic chipset connected to the host bus and the random access memory bus;

    said core logic chipset comprising;

    an accelerated graphics port (AGP) request queue;

    an AGP reply queue;

    an AGP data and control logic;

    an arbiter;

    an FC-AL request queue;

    an FC-AL reply queue;

    an FC-AL control register;

    an FC-AL data direct memory access register;

    a PCI to PCI bridge;

    said AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic connected to said random access memory bus;

    said AGP data and control logic connected to said AGP request and reply queues;

    said AGP data and control logic connected to an AGP interface;

    said arbiter connection to said AGP interface;

    said AGP request and reply queues connected to a host bus interface, said host bus interface connected to said host bus;

    a host to PCI bus bridge connected to said host bus interface and connected to a primary PCI bus;

    said PCI to PCI bridge connected to said AGP interface, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to primary PCI bus bridge and said AGP data and control logic;

    said FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface;

    said FC-AL control register connected to said FC-AL request and reply queues;

    an FC-AL data direct memory access register connected to said FC-AL control register; and

    said arbiter, said FC-AL data direct memory access register and said FC-AL control register connected to an FC-AL interface, whereinsaid core logic chipset configured as an interface bridge between the host bus and said AGP interface if a first configuration signal is present, or as an interface bridge between the host bus and said FC-AL interface if a second configuration signal is present; and

    said core logic chipset configured as an interface bridge between the random access memory bus and said AGP interface if the first configuration signal is present, or as an interface bridge between the random access memory bus and said FC-AL interface if the second configuration signal is present.

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