Shielded bit line sensing scheme for nonvolatile semiconductor memory
First Claim
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1. A nonvolatile semiconductor memory comprising:
- a memory cell array having first and second memory cells;
a word line commonly connected to control gates of the first and the second memory cells;
a first bit line connected to a drain-side node of the first memory cell;
a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line;
a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and
a decoder for selecting the word line, outputting data in the first memory cell to the first bit line in the first data read and outputting data in the second memory cell to the second bit line in the second data read.
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Abstract
A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.
186 Citations
26 Claims
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1. A nonvolatile semiconductor memory comprising:
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a memory cell array having first and second memory cells; a word line commonly connected to control gates of the first and the second memory cells; a first bit line connected to a drain-side node of the first memory cell; a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line; a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for selecting the word line, outputting data in the first memory cell to the first bit line in the first data read and outputting data in the second memory cell to the second bit line in the second data read. - View Dependent Claims (2, 3, 4, 5)
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6. A nonvolatile semiconductor memory comprising:
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a memory cell array having first and second memory cells, the first memory cell being disposed adjacent to the second memory cell; a word line commonly connected to control gates of the first and second memory cells; a first bit line connected to a drain-side node of the first memory cell; a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line; a first source line connected to a source-side node of the first memory cell; and a second source line connected to a source-side node of the second memory cell and isolated from the first source line. - View Dependent Claims (7, 8, 9, 10)
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11. A nonvolatile semiconductor memory comprising:
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first and second NAND cell units constituted by NAND columns having a plurality of memory cells connected to one another in series and two select transistors each of which is connected to of both ends of the NAND columns; a first bit line connected to a drain-side node of the first NAND cell unit; a second bit line connected to a drain-side node of the second NAND cell unit and disposed adjacent to the first bit line; a switch circuit operated in a first data read in such a manner as to precharge the first bit line to a precharge potential followed by bringing the first bit line to a floating state and to fix the second bit line to a positive potential and operated in a second data read in such a manner as to precharge the second bit line to the precharge potential followed by bringing the second bit line to the floating state and to fix the first bit line to the positive potential; and a decoder for outputting data of one memory cell in the first NAND cell units to the first bit line in the first data read and outputting data of one memory cell in the second NAND cell units to the second bit line in the second data read. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A data read method of a nonvolatile semiconductor memory having a word line commonly connected to control gates of first and second memory cells, a first bit line connected to a drain-side node of the first memory cell and a second bit line connected to a drain-side node of the second memory cell and disposed adjacent to the first bit line,
comprising the steps of: -
precharging the first bit line to a precharge potential followed by bringing the first bit line to a floating state and outputting data of the first memory cell to the first bit line in a state in which the second bit line is fixed to a positive potential in a first data read; and precharging the second bit line to the precharge potential followed by bringing the second bit line to the floating state and outputting data of the second memory cell to the second bit line in a state in which the first bit line is fixed to the positive potential in a second data read. - View Dependent Claims (18, 19, 20, 21)
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22. A data read method of a nonvolatile semiconductor memory having a first bit line connected to a drain-side node of a first NAND cell unit and a second bit line connected to a drain-side node of a second NAND cell unit and disposed adjacent to the first bit line,
comprising the steps of: -
precharging the first bit line to a precharge potential followed by bringing the first bit line to a floating state and outputting data of one memory cell of the first NAND cell unit to the first bit line in a state in which the second bit line is fixed to a positive potential in a first data read, and precharging the second bit line to the precharge potential followed by bringing the second bit line to the floating state and outputting data of one memory cell in the second NAND cell unit to the second bit line in a state in which the first bit line is fixed to the positive potential in a second data read. - View Dependent Claims (23, 24, 25, 26)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsWatanabe, Hiroshi, Iwata, Yoshihisa, Sugiura, Yoshihisa
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Primary Examiner(s)Dinh, Son T.
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Application NumberUS09/207,929Time in Patent Office510 DaysField of Search365/203, 365/63, 365/230.03, 365/185.05, 365/185.17US Class Current365/185.17CPC Class CodesG11C 16/0483 comprising cells having sev...G11C 16/26 Sensing or reading circuits...
