Redundancy scheme providing improvements in redundant circuit access time and integrated circuit layout area

• US 6,058,052 A
• Filed: 08/21/1997
• Issued: 05/02/2000
• Est. Priority Date: 08/21/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Steadman, Martin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US08/915,984
• Time in Patent Office: 985 Days
• Field of Search: 365/200, 365/205, 365/203
• US Class Current: 365/200
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A circuit comprising a main memory array with a block of columns per data I/O, a main read/write block per block of columns, one or more spare memory columns, a bad address detector circuit per spare column, and a read/write block per spare column. A spare column may replace a defective column or cell in any of the blocks of columns. The spare column may be read from/written to via the main read/write block of the column it is replacing, or via its own dedicated read/write block to improve access times. The bad address detector can be configured with programmable elements to produce a control signal when the address of a defective memory element (cell or column) is applied. This signal is then used to disable the defective memory element (and read/write block) and enable a spare column (and read/write block) in its place. The present invention also comprises a recovery circuit on the local data lines (multiplexed to the addressed bitlines). The recovery circuit in the block with the defective column is activated during a spare access. This allows the memory to be tolerant of some of the faults normally combated with column disconnect fuses without the use of such fuses. The present invention also comprises a logic circuit that utilizes a signal synchronized to the address signals to improve the speed of operation of the redundancy scheme.

Claims

1. A circuit comprising:

two or more main memory elements;

a first sense amplifier and write driver configured to present information from and to said main memory elements;

a spare memory element;

a second sense amplifier and write driver configured to present information from and to said spare memory element on a pair of differential data lines; and

a logic circuit configured to (a) enable said second sense amplifier and (b) decouple at least one main memory element from said first sense amplifier in response to an address of a defective main memory element; and

an equalization circuit configured to equalize said pair of differential data lines only after a write operation.

2. The circuit according to claim 1 further comprising a postdecoder and a pass gate, each coupled to one of said main memory elements.

3. The circuit according to claim 1 wherein said main memory elements and said spare memory element each comprise a column.

4. The circuit according to claim 3 further comprising:

a spare sense amplifier logic circuit configured to receive a control signal and enable one or more of said spare memory cells in response thereto.

5. The circuit according to claim 3 further comprising one or more local data busses configured to couple said first sense amplifier to said two or more columns.

6. The circuit according to claim 1 further comprising a programmable storage element for storing said address of said defective main memory.

7. The circuit according to claim 1 wherein each of said spare columns further comprises a clock input for reducing delays.

8. The circuit according to claim 7 wherein each of said logic circuits further comprises a clock input for reducing delays.

9. A method for repairing defective memory elements in a memory array, comprising the steps of:

determining whether an address corresponds to a defective memory element;

enabling a spare memory element and a spare sense amplifier/write driver on a pair of differential data lines;

decoupling said defective memory element from a main sense amplifier/write driver configured to connect to said defective memory element; and

equalizing said pair of differential data lines only after a write operation.

10. A circuit comprising:

two or more main memory elements;

first means for presenting information from and to said main memory elements;

a spare memory element;

second means for presenting information from and to said spare memory element on a pair of differential data lines;

means for (a) enabling said second sense amplifier and (b) decoupling at least one main memory element from said first sense amplifier in response to an address of a defective main memory element stored in a reprogrammable element; and

means for equalizing said pair of differential data lines only after a write operation.