Method and apparatus for combined timing recovery, frame synchronization and frequency offset correction in a receiver
First Claim
1. A method for performing timing recovery, frame synchronization and frequency offset correction in a receiver comprising:
- sampling a received analog signal;
determining an average amplitude of a predetermined number of most recent samples;
determining a first correlation value that indicates when a synchronization sequence is received based on the average amplitude;
performing a frequency offset correction based on a second correlation value which is based on the average amplitude, wherein the first correlation value and the second correlation value are determined simultaneously; and
sampling incoming data at a fixed offset from an end of the synchronization sequence.
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Abstract
A method and apparatus for combined timing recovery, frame synchronization and frequency offset correction in a digital receiver is provided. In general, the present invention provides a pair of correlators that operate on a set of samples output by a discriminator. A positive correlator generates a positive correlation value and a negative correlator generates a negative correlation value. The positive and negative correlation values are used to determine frame synchronization, frequency offset and timing recovery values so that timing recovery, frame synchronization and frequency offset correction may be performed simultaneously.
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Citations
23 Claims
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1. A method for performing timing recovery, frame synchronization and frequency offset correction in a receiver comprising:
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sampling a received analog signal; determining an average amplitude of a predetermined number of most recent samples; determining a first correlation value that indicates when a synchronization sequence is received based on the average amplitude; performing a frequency offset correction based on a second correlation value which is based on the average amplitude, wherein the first correlation value and the second correlation value are determined simultaneously; and sampling incoming data at a fixed offset from an end of the synchronization sequence. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus for performing timing recovery, frame synchronization and frequency offset correction in a digital receiver, wherein the receiver samples a signal at a predetermined rate, the apparatus comprising:
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means for sampling a received analog signal; means for determining an average amplitude of a predetermined number of most recent samples; means for determining a correlation value that indicates when a synchronization sequence is received; means for performing frequency offset correction based on inputs used to determine the correlation value; and means for sampling incoming data at a fixed offset from an end of the synchronization sequence. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A circuit for performing timing recovery, frame synchronization and frequency offset correction in a digital receiver, the circuit comprising:
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a discriminator to sample a signal and to output a digital signal; an integrator to receive the digital signal and to generate an average amplitude of a predetermined number of most recent samples; a positive correlator coupled to the integrator, the positive correlator to generate a positive correlation value; a negative correlator coupled to the integrator, the negative correlator to generate a negative correlation value; a first summing circuit coupled to the positive correlator and to the negative correlator, the first summing circuit to subtract the negative correlation value from the positive correlation value; a threshold detector coupled to the first summing circuit, the th reshold detector to indicate frame synchronization when the output of the first summing circuit exceeds a predetermined value; a second summing circuit coupled to the positive correlator and to the negative correlator, the second summing circuit to add the positive correlation value to the negative correlation value; and an AFC circuit coupled to the second summing circuit, the AFC circuit to generate a frequency correction value in response to an output generated by the second summing circuit, wherein the frequency correction value is generated simultaneously with the frame synchronization, and further wherein a frequency offset value is generated simultaneously with the frequency correction value. - View Dependent Claims (22, 23)
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Specification