Interface hardware design using internal and external interfaces

• US 6,058,263 A
• Filed: 06/03/1996
• Issued: 05/02/2000
• Est. Priority Date: 06/03/1996
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Voth, David W.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/659,084
• Time in Patent Office: 1,429 Days
• Field of Search: 364/488-491, 364/260, 364/260.1, 364/260.2, 364/244.9, 395/500, 395/883, 395/884, 395/800.36, 395/800.37, 395/800.39, 395/830, 395/828, 395/831, 395/832, 395/500.46, 710/10, 710/8, 710/100, 710/102, 710/103, 710/104, 710/105
• US Class Current: 703/25
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A computer system includes a plurality of discrete computer components and an integrated circuit that interfaces between the discrete computer components. The integrated circuit has internal hardware interfaces corresponding to respective discrete computer components. The internal hardware interfaces are selected from a limited number of available pre-defined internal hardware interfaces for general kinds of computer components. The internal hardware interfaces are accessible only within the integrated circuit. The integrated circuit further includes component-specific hardware interfaces for connecting the individual discrete components to the selected pre-defined internal HDL interfaces. The component-specific hardware interfaces are designed individually for the different discrete computer components to interface the discrete components to the internal hardware interfaces. A development system is disclosed for use during development of such a computer system. The development system includes interconnections that allow functions to be easily moved from the integrated circuit to a system CPU.

Claims

1. A development system comprising:

a single-chip component interface having a plurality of sets of configurable and externally accessible signal lines;

a plurality of peripheral modules that are external to the single-chip component interface, each of the peripheral modules being connected to a respective unique set of the plurality of sets of configurable and externally-accessible signal lines, the peripheral modules also being connected in common to a common set of the configurable and externally-accessible signal lines;

a CPU module, wherein the CPU module has connections to all of the sets of configurable and externally-accessible signal lines;

the single-chip component interface having internal hardware interfaces corresponding to respective peripheral modules, the internal hardware interfaces being accessible only within the single-chip component interface, wherein the internal hardware interfaces are selected from a plurality of pre-defined internal hardware interfaces for general kinds of computer components;

the single-chip component interface further including interconnection logic between the internal hardware interfaces;

the single-chip component interface further including component-specific hardware interfaces for configuring the plurality of sets of configurable signal lines to which the peripheral modules are connected, the component-specific hardware interfaces connecting the peripheral modules to the internal hardware interfaces;

the component-specific hardware interfaces being designed individually for the different peripheral modules to interface the peripheral modules to the internal hardware interfaces;

wherein a CPU on the CPU module can be connected to any lines of the sets of the plurality of sets to control such interface lines in place of the single-chip component interface.

2. A development system as recited on claim 1, wherein the single-chip component inerface is a programmable gate array.

3. A development system as recited in claim 1, wherein the peripheral modules are removable and replaceable.

4. A development system comprising:

a logic module having a single-chip component interface, the single-chip component interface having internal hardware interfaces and a plurality of sets of configurable and externally-accessible interface lines, the internal hardware interfaces being accessible only within the single-chip component interface, wherein the internal hardware interfaces are selected from a plurality of pre-defined internal hardware interfaces for general kinds of computer components;

the single-chip component interface having component-specific hardware interfaces for connecting peripheral modules to the internal hardware interfaces;

a plurality of peripheral electrical connectors for connection to the peripheral modules, wherein a unique set of the plurality of sets of configurable interface lines is accessible through the peripheral electrical connectors by each of the peripheral modules respectively, and wherein a common set of the configurable and externally-accessible interface lines is accessible through the peripheral electrical connectors by all of the peripheral modules; and

one or more CPU electrical connectors for connection to a CPU module, wherein the sets of configurable interface lines are accessible through the one or more CPU electrical connectors, and wherein a CPU on the CPU module can be connected to any lines of the sets of interface lines to control such interface lines in place of the component interface hardware.

5. A development system as recited in claim 4, wherein the single-chip component interface is a gate array.