Apparatus and method for generating a serial data stream carrying data for multiple network switch ports for use by a physical transceiver

• US 6,058,427 A
• Filed: 12/18/1997
• Issued: 05/02/2000
• Est. Priority Date: 02/14/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Viswanath, Somnath, Chow, Peter Ka-Fai
• Primary Examiner(s): Maung, Zarni
• Assistant Examiner(s): Barot, Bharat
• Application Number:
  US08/993,569
• Time in Patent Office: 866 Days
• Field of Search: 709/213, 709/215, 709/230-231, 709/236, 709/238, 709/242-244, 370/375-377, 370/400-402
• US Class Current: 709/231
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H04L 12/1863 comprising mechanisms for improved reliability, e.g. status reports arrangements for detecting or preventing errors by carrying supervisory signal the return channel H04L1/16
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 12/467 Arrangements for supporting untagged frames, e.g. port-based VLANs
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/40 : Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/50 : Overload detection or protection within a single switching element
• CPC Class Codes: H04L 49/552 : by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 : including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04L 49/9084 : Reactions to storage capacity overflow
• CPC Class Codes: H04Q 2213/1316 : Service observation, testing
• CPC Class Codes: H04Q 2213/13162 : Fault indication and localisation
• CPC Class Codes: H04Q 3/54591 : Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Abstract

A network switch having multiple media access control (MAC) switch ports has a physical transceiver interface that generates a time-division multiplexed serial data stream and outputs the time-division multiplexed serial data stream to a physical layer transceiver serving a respective multiple number of network nodes. The physical transceiver interface is also configured for receiving a time-division multiplexed serial input stream from the physical transceiver according to another repeating sequence of time slots corresponding to the network switch ports, where each of the serial data streams between the physical transceiver interface and the physical layer transceiver are synchronized relative to a shared system clock and a shared reset signal. The physical transceiver interface includes a timing circuit that reconciles timing differences between the MAC switch ports and the transmission and reception of data packets by the physical layer transceiver on the network media, minimizing the necessity of buffering in the transceiver interface.

Claims

1. A method for outputting data from a network switch having a plurality of switch ports to a physical transceiver, comprising:

reading from each switch port into a physical transceiver interface a data element having a prescribed number of bits;

mapping the data elements into a first serial data stream having groups of significant bits for the data elements, each group comprising a corresponding one of the significant bits for each of the data elements in a prescribed sequence corresponding to the switch ports; and

outputting the first serial data stream from the physical transceiver interface to the physical transceiver based on a prescribed clocking protocol shared between the physical transceiver interface and the physical transceiver.

2. The method of claim 1, wherein the physical transceiver interface includes a plurality of registers for the switch ports, respectively, the reading step comprising:

sequentially reading the data elements from the respective switch ports;

converting the data for each corresponding data element into a parallel data element; and

sequentially storing each said parallel data element in the corresponding register.

3. The method of claim 2, wherein the mapping step comprises loading the parallel data elements from the respective registers into a parallel load/serial shift circuit in response to a load signal synchronized with the prescribed clocking protocol.

4. The method of claim 3, wherein the outputting step comprises outputting each group in the first serial data stream according to a shift signal having a first time interval and synchronized with the prescribed clocking protocol, the load signal having a second time interval corresponding to a multiple number of the first time interval based on a number of the switch ports.

5. The method of claim 1, further comprising:

supplying a clock signal to the physical transceiver interface and the physical transceiver;

selectively asserting a reset signal for the physical transceiver interface and the physical transceiver; and

starting the prescribed clocking protocol at a prescribed interval relative to the clock signal in response to the selective assertion of the reset signal.

6. The method of claim 5, wherein the outputting step comprises aligning the groups within the first serial data stream with the prescribed clocking protocol based on the clock signal and the reset signal.

7. The method of claim 1, further comprising:

reading from each said switch port a frame signal specifying a presence of valid data within each bit of the corresponding data element;

mapping the frame signals from the respective switch ports into a second serial data stream having significant bit groups, each significant bit group comprising the frame signals for the corresponding significant bits for the respective data elements in said prescribed sequence; and

outputting the second serial data stream to the physical transceiver synchronously with the first serial data stream.

8. The method of claim 7, further comprising receiving, according to the prescribed clocking protocol, a third serial data stream from the physical transceiver in a second prescribed sequence corresponding to the switch ports, the third serial data stream including data bits from data packets received by the transceiver and arranged in groups of significant bits for received data packets, each group having the corresponding significant bits arranged in the second prescribed sequence.

9. The method of claim 8, wherein the second prescribed sequence corresponds to the first prescribed sequence by a prescribed time-shifted interval.

10. The method of claim 8, further comprising:

converting the groups of the third serial data stream into respective parallel groups of received significant bits;

supplying the groups of received significant bits to respective multiplexers; and

sequentially outputting from the multiplexers a data element for a corresponding one of the switch ports.

11. The method of claim 10, further comprising receiving from the physical transceiver a fourth serial data stream synchronous with the third serial data stream and according to the second prescribed sequence, the fourth serial data stream including valid data bits specifying a presence of valid data for the corresponding bit in the third serial data stream.

12. The method of claim 11, further comprising:

recovering the valid data bits for each said data element of the corresponding one switch port; and

aligning said each data element with the corresponding valid data bits to recover the corresponding data packet received by the transceiver.

13. A method comprising:

storing data elements received from respective network switch ports in respective registers, each data element having a prescribed number of bits;

generating an output serial data stream having a repeating sequence of time slots corresponding to the network switch ports, respectively, each sequence of time slots corresponding to a significant bit of the data elements stored in the registers; and

outputting the output serial data stream to a physical transceiver based on a prescribed clocking protocol.

14. The method of claim 13, wherein the generating step comprises:

sequentially storing each data element received from the corresponding network switch port into the corresponding register at a first prescribed data rate;

simultaneously loading a serial shift circuit with the data elements stored in the respective registers at a second prescribed data rate corresponding to the first prescribed data rate and a number of the network switch ports; and

sequentially shifting one of the significant bits from the data elements in the serial shift circuit according to the repeating sequence of time slots to form the output serial data stream.

15. The method of claim 14, wherein the outputting step comprises initiating the outputting of the sequence of time slots a predetermined interval after termination of a reset signal based on the prescribed clocking protocol.

16. The method of claim 13, further comprising:

receiving an input serial data stream from the physical transceiver based on the prescribed clocking protocol, the input serial data stream having a second repeating sequence of time slots corresponding to packet data received by the physical transceiver for the network switch ports, respectively, each sequence of time slots corresponding to a significant bit of the corresponding packet data;

recovering for each network switch port the corresponding packet data from the input serial data stream;

receiving a signaling serial stream from the physical transceiver having said second repeating sequence of time slots corresponding to a signaling condition for the network switch ports, respectively;

aligning for each network switch port the corresponding packet data based on the corresponding signaling condition from the signaling serial stream.

17. The method of claim 16, further comprising:

receiving a carrier sense serial stream from the physical transceiver having said second repeating sequence of time slots corresponding to a carrier sense condition for the network switch ports, respectively; and

recovering the carrier sense conditions for the respective network switch ports based on the prescribed clocking protocol.

18. The method of claim 16, further comprising:

receiving a collision serial stream from the physical transceiver having said second repeating sequence of time slots corresponding to a detected collision condition for the network switch ports, respectively; and

recovering the detected collision conditions for the respective network switch ports based on the prescribed clocking protocol.

19. An interface for a network switch having network switch ports, comprising:

a transmit portion configured for outputting a first serial data stream having a first repeating prescribed sequence of time slots corresponding to data output from the respective network switch ports, each first sequence of time slots corresponding to a significant bit of the data from the network switch ports, the transmit portion outputting the serial data stream to a physical transceiver according to a prescribed clocking protocol;

a receive portion configured for receiving from the physical transceiver a second serial data stream having a second repeating prescribed sequence of time slots corresponding to packet data for the respective network switch ports, the receive portion outputting the packet data for the respective network switch ports based on the second repeating prescribed sequence of time slots and the prescribed clocking protocol; and

a timing circuit for synchronizing the first and second serial data streams relative to the interface and the physical transceiver according to the prescribed clocking protocol and the physical transceiver.

20. The interface of claim 19, wherein the transmit portion comprises:

a plurality of registers for storing data elements having a prescribed number of bits from the network switch ports, respectively; and

a parallel load/serial shift circuit configured for loading the data elements stored in the registers in response to a load signal from the timing circuit, the parallel load/serial shift circuit generating said first serial data stream, in response to a shift signal from the timing circuit, by sequentially shifting one of the significant bits from the loaded data elements according to the repeating sequence of time slots.

21. The interface of claim 20, wherein the timing circuit operates according to the prescribed clocking protocol by generating the shift signal at a prescribed interval following a supplied reset pulse in response to a supplied clock signal.

22. The interface of claim 19, wherein the receive portion is configured for receiving from the physical transceiver a third serial data stream having said second repeating prescribed sequence of time slots corresponding to validity data for the respective packet data, the receive portion comprising:

a serial to parallel converter configured for generating, from the second serial data stream, a group of parallel data from one of the second repeating prescribed sequence of time slots;

a plurality of demultiplexers for the significant bits of the packet data, respectively, each demultiplexer outputting the corresponding significant bit for a selected one of the network switch ports in response to a network switch port selection signal.

23. The interface of claim 22, wherein the receive portion comprises four of said demultiplexers for outputting a nibble of the packet data in response to the network switch port selection signal.