Self-terminating electrical socket

• US 6,058,444 A
• Filed: 10/02/1997
• Issued: 05/02/2000
• Est. Priority Date: 10/02/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Johnson, Brian
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US08/942,878
• Time in Patent Office: 943 Days
• Field of Search: 395/282, 395/281, 326/30, 439/188, 710/129, 710/131, 710/101, 710/102
• US Class Current: 710/301
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination

Abstract

A self terminating electrical socket is described which adjusts communication line termination circuit characteristics in response to a mate engaging the socket. Electrical and mechanical detection techniques are described for switching the termination circuitry from a first state to a second state. The electrical socket is particularly well suited for use in a described memory bus. Multiple termination circuits are described which have different electrical characteristics depending upon the population of the electrical socket.

Claims

1. An electrical socket comprising:

an electrical connection for receiving an externally provided electrical signal;

a termination circuit coupled to the connection for terminating the electrical signal transmitted to the electrical connection, the termination circuit having a first set of electrical characteristics when the socket is not engaged with a mate, and a second set of electrical characteristics when the socket is engaged with a mate; and

a detector for detecting when a mate is engaged with the socket and providing an output signal to the termination circuit for selecting the first or second set of electrical characteristics.

2. The electrical socket of claim 1 wherein the detector is a switch activated by the mate.

3. The electrical socket of claim 2 wherein the switch has contacts which are closed when the socket is empty, and are open when the socket is engaged with the mate.

4. The electrical socket of claim 2 wherein the switch has contacts which are open when the socket is empty, and are closed when the socket is engaged with the mate.

5. The electrical socket of claim 2 wherein the switch comprises a relay.

6. An electrical socket comprising:

an electrical connection for receiving an externally provided electrical signal;

a termination circuit coupled to the connection for terminating the electrical signal transmitted to the electrical connection, the termination circuit having a first set of electrical characteristics when the socket is not engaged with a mate, and a second set of electrical characteristics when the socket is engaged with a mate;

a switch activated by the mate for detecting when a mate is engaged with the socket and providing an output signal to the termination circuit for selecting the first or second set of electrical characteristics, wherein the switch comprises a cam located to contact the mate when the socket is engaged with a mate.

7. An electrical socket comprising:

an electrical connection for receiving an externally provided electrical signal;

a termination circuit coupled to the connection for terminating the electrical signal transmitted to the electrical connection, the termination circuit having a first set of electrical characteristics when the socket is not engaged with a mate, and a second set of electrical characteristics when the socket is engaged with a mate;

a switch activated by the mate for detecting when a mate is engaged with the socket and providing an output signal to the termination circuit for selecting the first or second set of electrical characteristics, wherein the switch comprises a photo diode and a light source positioned such that light from the light source is prevented from reaching the photo diode when the socket is engaged with a mate.

8. A memory bus comprising:

a plurality of sockets coupled to a data communication line;

a plurality of detectors associated with the plurality of sockets, each of the plurality of detectors provides an output indicating when an associated one of the plurality of sockets is engaged with a memory module; and

a termination circuit coupled to the data communication line, the termination circuit having a plurality of electrical characteristic states selectable based upon the outputs from the plurality of detectors.

9. The memory bus of claim 8 wherein the plurality of detectors comprise relays.

10. The memory bus of claim 8 wherein the plurality of detectors comprise logic circuitry for receiving a signal provided from the memory module.

11. The memory bus of claim 8 wherein the plurality of detectors comprise photo diodes and light sources positioned such that light from the light sources is prevented from reaching the photo diodes when the plurality of sockets are engaged with mates.

12. The memory bus of claim 8 wherein the detectors comprise a multiplex circuit for selecting one of the plurality of electrical characteristic states.

13. The memory bus of claim 8 wherein the detectors comprise a switch activated by the memory module.

14. The memory bus of claim 13 further comprising a transistor activated by the switch to select one of the plurality of electrical characteristic states.

15. The memory bus of claim 13 wherein the switch is a mechanical switch activated by engaging the memory module with a socket.

16. The memory bus of claim 15 wherein the switch comprises first and second electrical contacts which are positioned such that they are in contact to form an electrical path when a memory module is not engaged with the socket, and are not in contact to form the electrical path when the memory module is engaged with the socket.

17. The memory bus of claim 15 wherein the switch comprises first and second electrical contact fingers which are positioned such that they are in contact to form an electrical path when a memory module is not engaged with the socket, and are not in contact to form the electrical path when the memory module is engaged with the socket.

18. The memory bus of claim 15 wherein the switch comprises a cam located to contact the memory module when the socket is engaged with the memory module.

19. The memory bus of claim 15 wherein the switch comprises first and second electrical contacts which are positioned such that they are not in contact when a memory module is not engaged with the socket, and are coupled together through a conductor provided on the memory module to form an electrical path when a memory module is engaged with the socket.

20. A computer system comprising:

a processor;

a memory bus having communication lines coupled between the processor and a plurality of sockets, each of the sockets adapted to receive a memory module;

a plurality of switch devices located in proximity to the sockets such that each one of the switches provides a signal indicating when one of the sockets is engaged with a memory module; and

a plurality of termination circuits, each termination circuit coupled to a communication line and having multiple electrical characteristics which are selected in response to the signals provided by the plurality of switch devices.

21. The computer system of claim 20 wherein the switch devices are activated by the memory module to physically interrupt an electrical connection through the switch.

22. The computer system of claim 20 wherein the switch devices are activated by the memory module to electrically interrupt an electrical connection through the switch.

23. The computer system of claim 20 wherein the plurality of termination circuits comprise resistors.

24. A method of terminating a communication line coupled to multiple sockets, the method comprising:

coupling a termination circuit having a first set of electrical characteristics to the communication line;

engaging a memory module with one of the multiple sockets;

detecting when the memory module is engaged with the one of the multiple sockets; and

adjusting the termination circuit to have a second set of electrical characteristics in response to the step of detecting.

25. The method of claim 24 wherein detecting comprises interrupting electrical contacts with the memory module.

26. The method of claim 24 wherein detecting comprises coupling electrical contacts with the memory module.

27. The method of claim 24 wherein detecting comprises receiving a signal from the memory module.

28. The method of claim 24 wherein detecting comprises interrupting a light source with the memory module.

29. The method of claim 24 wherein adjusting the termination circuit comprises coupling an additional electrical components to the communication line.

30. The method of claim 24 wherein adjusting the termination circuit comprises decoupling an electrical component from the communication line.

31. The method of claim 24 wherein adjusting the termination circuit comprises controlling a multiplex circuit.