Memory cells configurable as CAM or RAM in programmable logic devices

• US 6,058,452 A
• Filed: 05/28/1999
• Issued: 05/02/2000
• Est. Priority Date: 05/01/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rangasayee, Krishna, Bielby, Robert N.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Verbrugge, Kevin
• Application Number:
  US09/321,671
• Time in Patent Office: 340 Days
• Field of Search: 365/49, 365/154, 365/189.07, 711/108
• US Class Current: 711/108
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A programmable logic device having content addressable memory is disclosed. In a preferred embodiment, the programmable logic device includes reconfigurable dual mode memory suitable for operating as a content addressable memory in a first mode and a random access memory in a second mode is disclosed. Mode control switch circuitry may be provided to selectively enable a user to configure the dual mode memory as either content addressable memory or random access memory.

Claims

1. An integrated circuit, comprising:

a dual mode function block programmably suitable for operating as a first type function block in a first mode and as a second type function block in a second mode, wherein each dual mode function block includes

a first type function cell arranged to perform a first type function,

a second type function cell arranged to perform a second type function, and

an isolation circuit for electrically decoupling the first type function cell from the second type function cell wherein the dual mode function block operates exclusively as the first type function block when the isolation circuit is not activated and wherein the dual mode function block operates exclusively as the second type function block when the isolation circuit is activated.

2. An integrated circuit as recited in claim 1 further comprising:

a plurality of dual mode function blocks; and

an array of programmably interconnected logic cells suitable for use in implementing programmed logic functions coupled to the plurality of dual mode function blocks.

3. An integrated circuit as recited in claim 2 further comprising a mode control switch circuit suitable for selectively activating the isolation circuit.

4. An integrated circuit as recited in claim 3, wherein the first type function is a content addressable memory function and wherein the second type function is a static random access memory function.

5. An integrated circuit as recited in claim 4 wherein the dual mode function block further comprises:

a data storage circuit for storing data;

a comparison circuit for comparing data stored in the data storage circuit with requested data; and

a match line for indicating whether the stored data and the requested data match.

6. An integrated circuit as recited in claim 5 wherein the isolation circuit electrically decouples the data storage circuit from the comparison circuit and match line in the second mode such that the dual mode function block operates as a static random access memory.

7. An integrated circuit as recited in claim 6 wherein the data storage circuit includes a first and a second output node and the comparison circuit includes a first and a second comparator circuit.

8. An integrated circuit as recited in claim 7 wherein the isolation circuit includes a first isolating device electrically coupling the first comparator circuit of the comparison circuit and the first output node of the data storage circuit and a second isolating device electrically coupling the second comparator circuit of the comparison circuit and the second output node of the data storage circuit, the first and second isolating devices each activated by way of the mode control switch circuit.

9. An integrated circuit as recited in claim 8, wherein the first isolating device and the second isolating device each include an n-channel transistor.

10. An integrated circuit as recited in claim 8, wherein the first isolating device and the second isolating device each include a p-channel transistor.

11. An integrated circuit as recited in claim 1, wherein the integrated circuit is a programmable logic device.

12. A method for causing an integrated circuit to operate as a content addressable memory device in a first mode and as a static random access memory device in a second mode, wherein the integrated circuit includes a dual mode memory block, the dual mode memory block including an array of dual mode memory cells, each dual mode memory cell being suitable for operating as a content addressable memory in a first mode and as a static random access memory in a second mode, wherein each dual mode memory cell includes a data storage circuit for storing data, a comparison circuit for comparing data stored in the data storage circuit with requested data, and a match line for indicating whether the stored data and the requested data match, wherein each dual mode memory cell is coupled to an isolation circuit for electrically decoupling the data storage circuit from the comparison circuit and match line, the isolation circuit, in turn, being coupled to a mode control switch circuit suitable for selectively enabling the dual mode memory cells to operate in either the first or second modes, comprising:

providing a second mode select signal to the isolation circuit by the mode control switch circuit; and

activating the isolation circuit by second mode select signal such that the isolation circuit electrically decouples the data storage circuit from the comparison circuit in such a way that the dual mode memory cell operates exclusively as a static random access memory device.

13. A method as recited in claim 12, wherein the data storage circuit includes a first and a second output node and the comparison circuit includes a first and a second comparator circuit.

14. A method as recited in claim 12, wherein the isolation circuit includes a first isolating device electrically coupling the first comparator circuit of the comparison circuit and the first output node of the data storage circuit and a second isolating device electrically coupling the second comparator circuit of the comparison circuit and the second output node of the data storage circuit, the first and second isolating devices each activated by way of the mode control switch circuit.

15. A method as recited in claim 14, wherein the first isolating device and the second isolating device are each includes an n-channel transistor.

16. A method as recited in claim 14, wherein the first isolating device and the second isolating device are each includes a p-channel transistor.

17. A method as recited in claim 16, wherein the integrated circuit further comprises a plurality of programmable logic units coupled to the dual mode memory block.

18. A method as recited in claim 17, wherein the integrated circuit is a programmable logic device.