Video/audio decompression/compression device including an arbiter and method for accessing a shared memory

• US 6,058,459 A
• Filed: 08/26/1996
• Issued: 05/02/2000
• Est. Priority Date: 08/26/1996
• Status: Expired due to Term

• Current Assignee: Parthenon Unified Memory Architecture LLC (Acacia Research Corporation)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Colavin, Osvaldo, Owen, Jefferson Eugene, Diaz, Raul Zegers
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/702,910
• Time in Patent Office: 1,345 Days
• Field of Search: 395/888, 395/200.77, 395/293, 395/299, 711/147, 711/158, 711/151, 345/511, 345/512, 345/202, 709/247, 710/68, 710/113, 710/119
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/443 OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02

Abstract

An electronic system provides direct access between a first device and a decoder/encoder and a memory. The electronic system can be included in a computer in which case the memory is a main memory. Direct access is accomplished through one or more memory interfaces. Direct access is also accomplished in some embodiments by direct coupling of the memory to a bus, and in other embodiments, by direct coupling of the first device and decoder/encoder to a bus. The electronic system includes an arbiter for determining access for the first device and/or the decoder/encoder to the memory for each access request. The arbiter may be monolithically integrated into a memory interface of the decoder/encoder or the first device. The decoder may be a video decoder configured to decode a bit stream formatted to comply with the MPEG-2 standard. The memory may store predicted images which are obtained from a single preceding image and may also store intra images. Bidirectional images which are directly supplied to a display adapter may be obtained from two preceding intra or predicted images.

Claims

1. An electronic system comprising:

a first bus;

a first memory communicatively linked to the first bus;

a first device communicatively linked to the first bus to access the first memory, subject to a first device access control, through the first bus to the first memory without also requiring a second bus to access the first memory;

a decoder communicatively linked to the first bus to access the first memory, subject to a decoder access control, through the first bus to the first memory without also requiring a second bus to access the first memory; and

an arbiter communicatively linked to the first device for the first device access control, the arbiter communicatively linked to the decoder for the decoder access control, the arbiter configured to control access to the first memory for the first device and the decoder.

2. The electronic system of claim 1, further comprising a memory interface, the memory interface being communicatively linked to the decoder and to the first bus, the arbiter being monolithically integrated with the memory interface.

3. The electronic system of claim 1, further comprising a memory interface, the memory interface being communicatively linked to the first device and the first memory, the arbiter being monolithically integrated with the memory interface.

4. The electronic system of claim 1 wherein the arbiter comprises a cell or device separate from any monolithic integration of the first device or decoder.

5. The electronic system of claim 1 wherein the decoder comprises a video decoder.

6. The electronic system of claim 1 wherein the decoder is configured to decode a bitstream formatted to comply with the MPEG-2 standard.

7. The electronic system of claim 1, further comprising an encoder communicatively linked to the first bus, subject to an encoder access control, to access the first memory through the first bus without also requiring a second bus to access the first memory, the arbiter communicatively linked to the encoder for the encoder access control, the arbiter configured to control access to the first memory for the encoder.

8. The electronic system of claim 7 wherein the encoder is configured to produce a bitstream that complies with the H.263 standard.

9. The electronic system of claim 1 wherein the arbiter controls access to the first memory for at least the first device and the decoder based upon requests from the first device and from the decoder to access the first memory.

10. The electronic system of claim 1 wherein the first bus comprises either a PCI bus or a memory bus.

11. A computer comprising:

a first bus;

a first device communicatively linked to the first bus;

a decoder communicatively linked to the first bus;

a memory interface communicatively linked to the first bus, the memory interface comprising an arbiter; and

a first memory communicatively linked to the memory interface such that the first device and the decoder have access to the first memory without requiring a second bus for the first device or the decoder to access the first memory, the access of the first device and the decoder to the first memory being controlled by the arbiter based at least upon requests of the first device and the decoder to access the first memory.

12. The computer of claim 11 wherein the decoder comprises a video decoder.

13. The computer of claim 11, further comprising an encoder communicatively linked to the first bus to access the first memory through the memory interface without requiring a second bus for the encoder to access the first memory, the access of the encoder to the first memory being controlled by the arbiter based at least upon requests of the first device, the decoder, and the encoder to access the first memory.

14. The electronic system of claim 11 wherein the first device is either a chipset or a graphics accelerator.

15. The electronic system of claim 11 wherein the first bus is either a PCI bus or a memory bus.

16. In an electronic system a method comprising:

providing a first memory;

providing a first device;

providing a first bus;

providing a decoder;

communicatively linking the first memory to the first bus;

communicatively linking the first device to the first bus to access the first memory, subject to a first device access control, without requiring use of a second bus;

communicatively linking the decoder to the first bus to access the first memory, subject to a first device access control, without requiring use of a second bus;

providing an arbiter having an idle, a busy and a queue state;

communicatively linking the arbiter to the first device for the first device access control;

communicatively linking the arbiter to the decoder for the decoder access control;

generating a request by the decoder to access the first memory;

determining the state of the arbiter;

providing decoder access control so that the decoder can access the first memory, responsive to the arbiter being in the idle state;

queuing the request, responsive to the arbiter being in the busy state; and

queuing the request, responsive to the arbiter being in the queue state in an order responsive to the priority of the decoder request and the priority of any other queued requests.

17. The method of claim 16, further comprising the steps of:

determining the number of requests issued simultaneously;

responsive to the number of requests issued simultaneously being greater than one;

selectively providing access to the first memory responsive to the arbiter being in the idle state, and the priority of the simultaneously issued requests;

queuing the simultaneously issued requests responsive to the arbiter being in the busy state in an order responsive to the priority of the simultaneously issued requests; and

queuing the simultaneously issued requests responsive to the arbiter being in the queue state in an order responsive to the priority of the simultaneously issued requests and the priority of any other queued requests.

18. The method of claim 16, wherein the step of determining the number of requests issued simultaneously is performed prior to the step of determining the state of the arbiter.

19. The method of claim 16, further comprising the step of preempting the first device access to the first memory and providing the decoder access to the first memory responsive to the first device having a burst length above a burst length threshold.

20. The method of claim 16, wherein the decoder priority increases responsive to the length of time the request issued by the decoder is queued.