Method and apparatus for design verification using emulation and simulation

• US 6,058,492 A
• Filed: 11/12/1998
• Issued: 05/02/2000
• Est. Priority Date: 10/17/1996
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Bershteyn, Mikhail, Sample, Stephen P.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Baderman, Scott T.
• Application Number:
  US09/191,228
• Time in Patent Office: 537 Days
• Field of Search: 714/33, 714/28, 714/29, 714/37, 714/741, 364/232.3, 364/933.8, 364/488, 364/489, 364/578
• US Class Current: 714/33
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

Claims

1. An apparatus for verification of a user'"'"'s logic design comprising:

a plurality of first reconfigurable logic devices interconnected by a programmable interconnect, said plurality of reconfigurable logic devices and said programmable interconnect used for emulation of at least a portion of said user'"'"'s logic design;

at least one simulation module, said at least one simulation module comprising a microprocessor, a memory device, and a second reconfigurable logic device, said microprocessor, said memory device and said second reconfigurable logic device in communication with each other through a data bus, said at least one simulation module used for simulation of at least a portion of said user'"'"'s logic design; and

an event detector in electrical communication with said at least one simulation module for detecting events taking place during verification.

2. The apparatus of claim 1 further comprising a scheduler for scheduling operations that said microprocessor would ordinarily schedule.

3. The apparatus of claim 1 wherein said at least one simulation module further comprises a second microprocessor.

4. The apparatus of claim 1 further comprising a bus controller in electrical communication with said microprocessor.

5. The apparatus of claim 1 wherein each of said plurality of first reconfigurable logic devices comprise a field programmable gate array.

6. The apparatus of claim 5 wherein said second reconfigurable logic device comprises a field programmable gate array.

7. The apparatus of claim 6 wherein each of said plurality of first reconfigurable logic devices and said second reconfigurable logic device comprise identical field programmable gate arrays.