Logic circuit emulator
First Claim
1. An apparatus for simulating a logic circuit according to simulated clock cycles initiated by clock signals, said apparatus comprising:
- a first plurality of logic block circuits for simulating portions of said logic circuit upon receipt of a clock signal for a simulated clock cycle, said logic block circuits further having a predetermined number of signal inputs and outputs;
at least one routing block for routing signals between said logic block circuits between said simulated clock cycles; and
each of said logic block circuits further including;
a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding said logic block circuit at an end of said simulated clock cycle; and
a second series of input scan chain units for storing and inputting a signal for each of said logic block units at a beginning of said simulated clock cycle;
each of said scan chain units being further interconnected to said routing logic block for storing of said input signals and said output signals to and from said routing;
logic block between said simulated clock cycles.
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Abstract
An apparatus for simulating a logic circuit is disclosed comprising a first plurality of logic block circuits for simulating portions of the logic circuit the logic block circuits having a predetermined number of inputs and outputs; at least one routing logic block for routing signals between the logic block circuits; each of the logic block circuits further including: a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding the logic block circuit; and a second series of input scan chain units for storing and inputting a signal to each of the logic block inputs; each of the scan chain units being further interconnected to the routing logic block for the storing of the input signals and the output signals to and from the routing logic block. Further, the scan chain units can preferably comprise a series of serially interconnected storage units and the interconnection of the routing logic can preferably comprise a serial interconnection between one of the storage units and the routing logic. Ideally, the storage units comprise flip flops each interconnected to a master clock signal input. The output scan chain units can include a multiplexer connected between the signal outputs and a corresponding storage unit the multiplexer multiplexing the signal output and the output of an adjacent storage unit.
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Citations
12 Claims
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1. An apparatus for simulating a logic circuit according to simulated clock cycles initiated by clock signals, said apparatus comprising:
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a first plurality of logic block circuits for simulating portions of said logic circuit upon receipt of a clock signal for a simulated clock cycle, said logic block circuits further having a predetermined number of signal inputs and outputs; at least one routing block for routing signals between said logic block circuits between said simulated clock cycles; and each of said logic block circuits further including; a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding said logic block circuit at an end of said simulated clock cycle; and
a second series of input scan chain units for storing and inputting a signal for each of said logic block units at a beginning of said simulated clock cycle;each of said scan chain units being further interconnected to said routing logic block for storing of said input signals and said output signals to and from said routing;
logic block between said simulated clock cycles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A configurable digital system for simulating a logic circuit according to simulated clock cycles initiated by clock signals, said system comprising:
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a plurality of digital components each having a predetermined number of input and output pins for performing algorithmic functions on signal inputs upon receipt of a clock signal for a simulated clock cycle; a plurality of sample storage devices to sample a value of said output pins at the end of said simulated clock cycle; and a routing system to store and transfer, in a time multiplexed fashion, the values sampled by said sample storage devices for forwarding to a predetermined input pin before a beginning of a next said simulated clock cycle; whereby over many simulated clock cycles the emulation of the operation of said logic circuit is achieved.
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12. A method of emulating a logic circuit according to simulated clock cycles initiated by clock signals, the method comprising the steps of:
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(a) dividing said logic circuits into a series of logic blocks each having predetermined inputs and outputs; (b) simulating the operation of each of said series of logic blocks during a first simulated clock cycle; (c) storing the said outputs of each of said series of logic blocks at an end of said first simulated clock cycle; (d) distributing said outputs to predetermined ones of said inputs to said series of logic blocks before a start of a subsequent simulated clock cycle; and (e) iteratively repeating said steps (b) to (d) so as to emulate the operation of said logic circuit.
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Specification
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- Resources
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Current AssigneeVincenzo Arturo Luca Liguori
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Original AssigneeVincenzo Arturo Luca Liguori
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InventorsLiguori, Vincenzo Arturo Luca
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Primary Examiner(s)Teska, Kevin J.
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Assistant Examiner(s)Knox, Lonnie A.
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Application NumberUS09/014,359Time in Patent Office833 DaysField of Search371/22.3, 371/22.1, 371/22.5, 371/22.6, 395/500.43, 395/500.44, 395/500.17, 395/500.49US Class Current703/23CPC Class CodesG06F 30/331 with hardware acceleration,...
