Method of manufacture of P-channel EEprom and flash EEprom devices

• US 6,060,360 A
• Filed: 04/14/1997
• Issued: 05/09/2000
• Est. Priority Date: 04/14/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Shiou-Hann, Kuo, Di-Son, Lin, Yai-Fen, Yeh, Juang-Ke
• Primary Examiner(s): Booth, Richard
• Application Number:
  US08/843,183
• Time in Patent Office: 1,121 Days
• Field of Search: 438/257-267, 438/593, 438/594
• US Class Current: 438/264
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel

Abstract

A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

Claims

1. A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate comprising an N-well doped with a first, N-type of dopant, by the steps comprising:

forming a tunnel oxide layer over said substrate,

then forming a floating gate electrode layer comprising a polysilicon layer over said tunnel oxide layer and then doping said floating gate electrode layer with said first, N-type of dopant,

then forming an interelectrode dielectric layer over said floating gate electrode,

then forming a control gate electrode layer including a layer composed of polysilicon over said interelectrode dielectric layer and then counterdoping said control gate electrode with an opposite, P-type of dopant,

then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer and, said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, and

then performing an ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite, P-type of source/drain dopant symmetrically self-aligned with said gate electrode stack,

whereby said source region and said drain region are self-aligned with said gate electrode stack.

2. The method of claim 1 wherein:

said floating gate electrode layer is a laminated structure comprising;

an undoped lower polysilicon layer,

said doped polysilicon layer formed on said lower polysilicon layer, and

an undoped upper polysilicon layer formed on said doped polysilicon layer.

3. The method of claim 1 wherein:

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

4. The method of claim 1 wherein:

said floating gate electrode layer has a thickness from about 1,000 Å

to about 1,200 Å

.

5. The method of claim 1 wherein said floating gate electrode layer is a laminated structure comprising:

a lower, undoped polysilicon layer having a thickness from about 1,000 Å

to about 1200 Å

,

an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å

to about 1200 Å

, and

an upper, undoped polysilicon layer having a thickness from about 2,000 Å

to about 3,000 Å

.

6. The method of claim 1 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer,

an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, and said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

.

7. The method of claim 1 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer,

an N+ doped polysilicon layer formed on said lower polysilicon layer, and

an undoped upper polysilicon layer,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

8. The method of claim 1 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

,

an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

, and

an undoped upper polysilicon layer having a thickness from about 2,000 Å

to about 3,000 Å

,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

9. The method of claim 1 wherein:

said floating gate electrode layer is a laminated structure comprising a lower polysilicon undoped layer having a thickness from about 1,000 Å

to about 1,200 Å

, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

, and an undoped upper polysilicon layer having a thickness from about 2,000 Å

to about 3,000 Å

,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said sour ce/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm², and

said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm² to about 1.4 E 13 ions/cm².

10. A method of forming a split gate FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant, said device having a channel, said channel having a channel width, by the steps comprising:

forming a tunnel oxide layer over said substrate,

then forming a floating gate electrode layer including a first doped polysilicon layer with said first type of dopant over said tunnel oxide layer,

patterning said floating gate electrode layer into a split gate floating gate electrode have a narrower width than said channel width,

then forming an interelectrode dielectric layer over said floating gate electrode and the exposed portion of said tunnel oxide,

then forming a control gate electrode layer including a layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer,

then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layer, thereby patterning said tunnel oxide layer, said floating gate electrode layer, said interelectrode dielectric layer, and said control gate electrode into a gate electrode stack above said channel, and

then performing a self-aligned ion implanting doping step in which a source region and a drain region in said surface of said substrate are doped with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack,

whereby said source region and said drain region are self-aligned with said gate electrode stack of said split gate FET semiconductor device.

11. The method of claim 10 wherein said floating gate electrode layer is a laminated structure comprising:

an undoped lower polysilicon layer,

said first doped polysilicon layer formed on said lower polysilicon layer, and

an undoped upper polysilicon layer formed on said counterdoped polysilicon layer.

12. The method of claim 10 wherein:

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

13. The method of claim 10 wherein:

said floating gate electrode layer has a thickness from about 1,000 Å

to about 1,200 Å

.

14. The method of claim 10 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

, a doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

, and

an undoped upper polysilicon layer having a thickness from about 2,000 Å

to about 3,000 Å

.

15. The method of claim 10 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer,

a doped polysilicon layer formed on said lower polysilicon layer, and

an undoped upper polysilicon layer, and

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

.

16. The method of claim 10 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer, a doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

17. The method of claim 10 wherein:

said floating gate electrode layer is a laminated structure comprising an undoped lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

, an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

,

and an undoped upper polysilicon layer having a thickness from about 2,000 Å

to about 3,000 Å

,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

18. The method of claim 10 wherein:

said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm² to about 1.4 E 13 ions/cm².

19. A method of forming an FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant by the steps comprising:

forming a tunnel oxide layer over said substrate,

then forming floating gate electrode layers over said tunnel oxide layer, by the steps comprising;

a) forming a lower, undoped polysilicon layer,

b) then forming a doped polysilicon layer formed on said lower polysilicon layer doped with said first type of dopant, and

c) then forming an upper, undoped polysilicon layer formed on said doped polysilicon layer,

then forming an interelectrode dielectric layer over said floating gate electrode layers,

then forming a control gate electrode layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer,

then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack, and

then performing a self-aligned ion implanting doping step in which a source region and a drain region are formed by doping into said surface of said substrate with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack,

whereby said source region and said drain region are self-aligned with said gate electrode stack.

20. The method of claim 19 wherein:

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

21. The method of claim 19 wherein said doped floating gate electrode layer has a thickness from about 1,000 Å

to about 1,200 Å

.

22. The method of claim 19 wherein said floating gate electrode layers are a laminated structure comprising:

said lower, undoped polysilicon layer which has a thickness from about 1,000 Å

to about 1200 Å

,

said N+ doped polysilicon layer which has a thickness from about 1,000 Å

to about 1200 Å

, and

said upper, undoped polysilicon layer which has a thickness from about 2,000 Å

to about 3,000 Å

.

23. The method of claim 19 wherein:

said floating gate electrode layers are a laminated structure comprising an undoped lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer, and

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

.

24. The method of claim 19 wherein:

said floating gate electrode layers are a laminated structure comprising an undoped lower polysilicon layer, an N+ doped polysilicon layer formed on said lower polysilicon layer, and an undoped upper polysilicon layer,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

25. The method of claim 19 wherein:

said floating gate electrode layers are a laminated structure comprising;

a) an undoped lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

,

b) an N+ doped polysilicon layer formed on said lower polysilicon layer having a thickness from about 1,000 Å

to about 1,200 Å

, and

e) an undoped upper polysilicon layer having a thickness from about 2,000 Å

to about 3,000 Å

,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

26. The method of claim 19 wherein:

said floating gate electrode layers are a laminated structure comprising;

a) said lower polysilicon undoped layer which has a thickness from about 1,000 Å

to about 1,200 Å

,

b) said doped polysilicon layer formed on said lower polysilicon layer which has a thickness from about 1,000 Å

to about 1,200 Å

, and

c) said undoped upper polysilicon layer which has a thickness from about 2,000 Å

to about 3,000 Å

,

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm², and

said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm² to about 1.4 E 13 ions/cm².

27. A method of forming a split gate FET semiconductor device in a doped silicon semiconductor substrate having a surface, said substrate being doped with a first type of dopant, said device having a channel, said channel having a channel width, by the steps comprising:

forming a tunnel oxide layer over said substrate,

then forming floating gate electrode layers over said tunnel oxide layer, comprising forming a lower, undoped polysilicon layer, forming a doped polysilicon layer doped with said first type of dopant on said lower polysilicon layer, and forming an upper, undoped polysilicon layer formed on said doped polysilicon layer,

patterning said floating gate electrode layer into a split gate floating gate electrode have a narrower width than said channel width,

then forming an interelectrode dielectric layer over said floating gate electrode layers and the exposed portion of said tunnel oxide,

then forming a control gate electrode including a layer composed of polysilicon counterdoped with an opposite type of dopant from said first type of dopant over said interelectrode dielectric layer,

then forming a mask and etching away exposed portions of said control gate electrode layer, said interelectrode dielectric layer, and said floating gate electrode layers thereby patterning said tunnel oxide layer, said floating gate electrode layers, said interelectrode dielectric layer, and said control gate electrode layer into a gate electrode stack above said channel, and

then performing a self-aligned ion implanting doping step in which a source region and a drain region are forming by doping into said surface of said substrate with said opposite type of source/drain dopant symmetrically self-aligned with said gate electrode stack, and

whereby said source region and said drain region are self-aligned with said gate electrode stack of said split gate FET semiconductor device.

28. The method of claim 27 wherein:

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

29. The method of claim 27 wherein:

said floating gate electrode layer has a thickness from about 1,000 Å

to about 1,200 Å

.

30. The method of claim 27 wherein:

said floating gate electrode layers are a laminated structure comprising;

an undoped lower polysilicon layer which has a thickness from about 1,000 Å

to about 1,200 Å

,

a doped polysilicon layer formed on said lower polysilicon layer which has a thickness from about 1,000 Å

to about 1,200 Å

, and

an undoped upper polysilicon layer which has a thickness from about 2,000 Å

to about 3,000 Å

.

31. The method of claim 27 wherein:

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

.

32. The method of claim 27 wherein:

said tunnel oxide layer has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

33. The method of claim 27 wherein:

said floating gate electrode layers are a laminated structure comprising;

said undoped lower polysilicon layer which has a thickness from about 1,000 Å

to about 1,200 Å

,

said doped polysilicon layer formed on said lower polysilicon layer which has a thickness from about 1,000 Å

to about 1,200 Å

, and

said undoped upper polysilicon layer which has a thickness from about 2,000 Å

to about 3,000 Å

,

said tunnel oxide layer which has a thickness from about 90 Å

to about 100 Å

, and

said source/drain dopant comprises P type dopant ions of boron fluoride, BF₂, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm² to about 5 E 15 ions/cm².

34. The method of claim 27 wherein:

said substrate is doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm² to about 1.4 E 13 ions/cm².