Methods of fabricating field effect transistors including side branch grooves

• US 6,060,362 A
• Filed: 06/09/1998
• Issued: 05/09/2000
• Est. Priority Date: 08/08/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Rhee, Tae-Pok
• Primary Examiner(s): Elms, Richard T.
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US09/094,291
• Time in Patent Office: 700 Days
• Field of Search: 438/301, 438/305, 438/306, 438/321, 438/377, 438/699, 438/926, 438/264
• US Class Current: 438/301
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A field effect transistor includes radially extending grooves in a microelectronic substrate. At least one of the radially extending grooves includes a side branch groove extending from it. A ring-shaped gate is included on the radially extending grooves. The ring-shaped gate defines inner and outer regions of the microelectronic substrate. Source and drain regions are included in the respective inner and outer regions of the microelectronic substrate. The side branch grooves may be used to decrease on-state resistance and increase drive current of the field effect transistor.

Claims

1. A method of forming a field effect transistor comprising the steps of:

forming a plurality of radially extending grooves in a microelectronic substrate, at least one of the radially extending grooves including a side branch groove extending therefrom;

forming a ring-shaped gate on the radially extending grooves including on the at least one side branch groove; and

forming spaced apart source and drain regions in the microelectronic substrate.

2. A method according to claim 1 wherein the step of forming a ring shaped gate defines inner and outer regions of the microelectronic substrate, and wherein the step of forming spaced apart source and drain regions comprises the step of:

forming a source region in the inner region of the microelectronic substrate and a drain region in the outer region of the microelectronic substrate.

3. A method according to claim 1 wherein the groove forming step comprises the step of forming radially extending grooves arranged in a circle, wherein alternating ones of the radially extending grooves includes a side branch groove extending therefrom.

4. A method according to claim 1 wherein the groove forming step comprises the step of forming radially extending grooves arranged in a square which defines four corner grooves, and wherein the four corner grooves each includes a side branch groove extending therefrom.

5. A method according to claim 1 wherein the groove forming step comprises the step of forming radially extending grooves arranged in a square which defines four sides of grooves, wherein the end grooves of adjacent sides are joined to define four common vertices, and wherein the four common vertices each includes a side branch groove extending therefrom.

6. A method according to claim 1 wherein the ring-shaped gate forming step comprises the step of:

forming a gate insulating layer on the radially extending grooves including on the at least one side branch groove; and

forming a ring shaped gate electrode on the gate insulating layer, opposite the radially extending grooves and the at least one side branch groove.

7. A method according to claim 1 wherein groove forming step comprises the step of forming a plurality of radially extending grooves in a microelectronic substrate, at least one of the radially extending grooves including a side branch groove extending therefrom, the radially extending grooves and the at least one side branch groove being U-shaped, V-shaped or arcuate in cross section.