Process for forming re-entrant geometry for gate electrode of integrated circuit structure

• US 6,060,375 A
• Filed: 07/31/1996
• Issued: 05/09/2000
• Est. Priority Date: 07/31/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Owyang, Jon, Aronowitz, Sheldon, Kimball, James P.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): NGUYEN, HA T
• Application Number:
  US08/690,577
• Time in Patent Office: 1,378 Days
• Field of Search: 438/585, 438/657, 438/659, 438/673, 438/719, 438/739, 438/302, 438/735, 438/741
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape

Abstract

A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180° and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e., some lying along an X axis in the plane of the masked polysilicon layer on the substrate and others lying along a Y axis in the plane of the masked polysilicon layer on the substrate, the substrate may be rotated 90°, rather than 180°, between each implantation, and four implantations, rather than two, are performed. After the implantations, the implanted masked polysilicon layer is then subject to an etch, preferably an anisotropic etch, which will remove the unmasked implanted portions of the polysilicon layer, as well as the implanted regions beneath the mask, resulting in a gate electrode with re-entrant or tapered sidewalls, i.e., resembling an inverted trapezoid in cross-section.

Claims

1. A process for forming a re-entrant polysilicon gate electrode over a substrate for an integrated circuit structure having a tapered sidewall extending to a narrowed base which comprises:

a) selectively implanting a polysilicon layer beneath a gate electrode mask to promote undercutting of said mask during subsequent etching of said polysilicon layer to form said gate electrode; and

b) then anisotropically etching said polysilicon layer to remove unmasked portions of said polysilicon layer and implanted portions of said polysilicon layer beneath said mask to form said re-entrant polysilicon gate electrode.

2. The process of claim 1 wherein said polysilicon layer beneath said mask is implanted by tilting said substrate and said polysilicon layer thereover with respect to the axis of an implantation beam used to implant said substrate.

3. The process of claim 2 wherein said polysilicon layer beneath said mask is implanted with an element selected from the group consisting of Group IV and Group VIII elements.

4. The process of claim 3 wherein said polysilicon layer beneath said mask is implanted with said element at a dosage level sufficient to change the crystalline state of the implanted portion of said polysilicon layer to an amorphous state.

5. The process of claim 4 wherein said polysilicon layer beneath said mask is implanted with an element selected from the group consisting of silicon and argon.

6. The process of claim 2 wherein said polysilicon layer beneath said mask is implanted by tilting said substrate and said polysilicon layer thereover with respect to the axis of an implantation beam used to implant said substrate an amount ranging from about 5°

to about 30°

.

7. The process of claim 4 wherein said polysilicon layer beneath said mask is implanted by tilting said substrate and said polysilicon layer thereover with respect to the axis of an implantation beam used to implant said substrate at an angle of about 6°

.

8. The process of claim 4 wherein said polysilicon layer beneath said mask is implanted at an energy insufficient to damage said gate oxide layer beneath said polysilicon layer.

9. The process of claim 4 wherein said polysilicon layer beneath said mask is implanted with an element selected from the group consisting of Group IV and Group VIII elements at a dosage level sufficient to change the crystalline state of the implanted portion of said polysilicon layer to an amorphous state and at an energy level insufficient to damage said gate oxide layer beneath said polysilicon layer.

10. A process for forming a re-entrant polysilicon gate electrode over a substrate for an integrated circuit structure having a tapered sidewall extending to a narrowed base which comprises:

a) tilting a substrate, having a polysilicon layer thereon with a gate electrode mask formed over said polysilicon layer, at an angle, with respect to the axis of an implantation beam, ranging from about 5°

to about 30°

;

b) selectively implanting said polysilicon layer beneath said gate electrode mask with an element selected from the group consisting of Group IV and Group VIII elements and at a dosage level sufficient to change the crystalline state of the implanted portion of said polysilicon layer to an amorphous state to promote undercutting of said mask during subsequent etching of said polysilicon layer to form said gate electrode; and

c) then anisotropically etching said polysilicon layer to remove unmasked portions of said polysilicon layer and implanted portions of said polysilicon layer beneath said mask to form said re-entrant polysilicon gate electrode.

11. A process for forming a re-entrant polysilicon gate electrode over a semiconductor substrate for an integrated circuit structure having a tapered sidewall extending to a narrowed base which comprises:

a) forming a polysilicon gate electrode layer over a gate oxide layer on said semiconductor substrate;

b) forming a gate electrode mask over said polysilicon layer;

c) then selectively implanting said polysilicon layer beneath said gate electrode mask to promote undercutting of said mask at least adjacent said gate oxide layer during subsequent etching of said polysilicon layer to form said re-entrant polysilicon gate electrode; and

d) then anisotropically etching said polysilicon layer to remove unmasked portions of said polysilicon layer and implanted portions of said polysilicon layer beneath said mask to form said re-entrant polysilicon gate electrode;

whereby a re-entrant polysilicon gate electrode may be formed with a taper extending inwardly at the lower portion or base of the polysilicon electrode adjacent the underlying gate oxide to provide a polysilicon gate electrode resembling, in cross-section, an inverted trapezoid.

12. A process for forming a re-entrant polysilicon gate electrode over a semiconductor substrate for an integrated circuit structure having a tapered sidewall extending to a narrowed base which comprises:

a) forming a gate oxide layer over said semiconductor substrate;

b) forming a polysilicon gate electrode layer over said gate oxide layer;

c) forming a gate electrode mask over said polysilicon layer on said substrate;

d) tilting said substrate and said polysilicon layer thereover, with respect to the axis of an implantation beam used to implant said substrate, an amount ranging from about 5°

to about 30°

;

e) then selectively implanting said polysilicon layer beneath said gate electrode mask with said implantation beam to promote formation of a gate electrode sidewall tapering inwardly from said mask to said oxide layer beneath said polysilicon layer during subsequent etching of said polysilicon layer to form said gate electrode; and

f) then anisotropically etching said polysilicon layer to remove unmasked portions of said polysilicon layer and implanted portions of said polysilicon layer beneath said mask to form said tapered polysilicon gate electrode;

whereby a gate electrode may be formed with a taper extending inwardly at the lower portion or base of the polysilicon electrode adjacent the underlying gate oxide to provide a gate electrode resembling, in cross-section, an inverted trapezoid.

13. The process of claim 12 wherein said polysilicon layer beneath said mask is implanted by tilting said substrate and said polysilicon layer thereover with respect to the axis of an implantation beam used to implant said substrate an amount ranging from about 5°

to about 10°

.