Semiconductor device

• US 6,060,747 A
• Filed: 09/23/1998
• Issued: 05/09/2000
• Est. Priority Date: 09/30/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuchitani, Masanobu, Matsuda, Noboru, Okumura, Hideki, Baba, Yoshiro, Osawa, Akihiko
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/159,122
• Time in Patent Office: 594 Days
• Field of Search: 257/330-334, 257/341, 257/342, 438/270, 438/271, 438/589
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

Claims

1. A semiconductor device comprising:

a first conductivity type high-resistance layer;

a second conductivity type base layer formed on the first conductivity type high-resistance layer;

a first conductivity type source layer formed in a surface of the second conductivity type base layer, the first conductivity type source layer having a plurality of first opening portions, which are respectively formed on a plurality of points of intersection of an imaginary lattice diagonally arranged on the first conductivity source layer, and through which the second conductivity type base layer is exposed;

a plurality of trenches, each selectively formed, in a depth direction, so as to pass through the first conductivity type source layer and the second conductivity type base layer and extend to the first conductivity type high-resistance layer, and each formed so as to snake through between the plurality of first opening portions in one form selected from the group consisting of a zigzag line form and a fish bone form, as viewed from above;

a plurality of gate electrodes each being buried in a corresponding one of the plurality of trenches with a gate insulating film interposed therebetween;

an interlayer insulating film formed on the first conductivity type source layer, the interlayer insulating film having a plurality of second opening portions, each of which has a region formed of the second conductivity type base layer exposed in each of the first openings, and a region formed of the first conductivity type source layer next to the region formed of the second conductivity type base layer;

a source electrode formed on the interlayer insulating layer, the source electrode being in contact with the regions of the second conductivity type base layer exposed in the plurality of first opening portions and the regions of the first conductivity type source layer next thereto, through the second opening portions;

a drain layer formed on an opposite surface to a surface of said first conductivity type high-resistance layer having said second conductivity type base layer formed thereon; and

a drain electrode formed on said drain layer,

wherein each of the plurality of trenches is arranged substantially at a same distance from each of the plurality of first opening portions, the same distance being set at a minimum accessible value of distance between each of the trenches and adjacent one of the first opening portions.

2. The semiconductor device according to claim 1, wherein each of the plurality of trenches formed in the zigzag line has a square-pulse waveform configuration, as viewed from above.

3. The semiconductor device according to claim 1, wherein each of the plurality of trenches formed in the zigzag line has a trapezoidal pulse waveform configuration, as viewed from above.

4. The semiconductor device according to claim 1, wherein each of the plurality of trenches formed in the fish bone form has a main groove linearly extending among the plurality of first opening portions and a plurality of branched groove portions each being interposed between adjacent ones of the first opening portions along said main groove.

5. The semiconductor device according to claim 1, wherein the drain layer is formed of the first conductivity type semiconductor, thereby forming a MOSFET.

6. The semiconductor device according to claim 1, wherein the drain layer is formed of the second conductivity type semiconductor, thereby forming one of an IGBT and an IEGT.

7. A semiconductor device comprising:

a first conductivity type high-resistance layer;

a second conductivity type base layer formed on the first conductivity type high resistance layer;

a plurality of first conductivity type source layers formed in stripes in a surface of the second conductivity type base layer, each of the plurality of first conductivity type source layers having a plurality of first opening portions which are arranged in parallel to the stripes and through which the second conductivity type base layer is exposed;

a plurality of trenches, each being formed between adjacent two of the first conductivity type source layers, as viewed from above, and passing through the first conductivity type source layer and the second conductivity type base layer and extending to the first conductivity type high-resistance layer, in a depth direction;

a plurality of gate electrodes each being buried in a corresponding one of the plurality of trenches with a gate insulating film interposed therebetween;

an interlayer insulating film formed on the first conductivity type source layer and having a plurality of second opening portions, each of the plurality of second opening portions exposing the first opening portion, through which the second conductivity type base layer is exposed, and a region formed of the first conductivity type source layer surrounding the first opening portion;

a source electrode formed on the interlayer insulating layer, the source electrode being in contact with the plurality of second conductivity type base layers and the plurality of first conductivity type source layers through the plurality of second opening portions;

a drain layer formed on an opposite surface to a surface of the first conductivity type high-resistance layer having the second conductivity type base layer formed thereon; and

a drain electrode formed on the drain layer,

wherein the plurality of first openings which are arranged in adjacent two stripes of the plurality of first conductivity type source layers, are arranged staggeringly and alternately between the adjacent two stripes of the source layers, and one of the plurality of trenches formed between the adjacent two stripes of the source layers snakes in a zigzag line through the plurality of first opening portions arranged staggeringly.

8. The semiconductor device according to claim 7, wherein each of the plurality of trenches formed in the zigzag line, has a square waveform configuration, as viewed from above.

9. The semiconductor device according to claim 7, wherein each of the plurality of trenches formed in the zigzag line, has a trapezoidal pulse waveform configuration, as viewed from above.

10. The semiconductor device according to claim 7, wherein a distance T₁ between adjacent two of the trenches sandwiching one of the plurality of first opening portions is larger than a distance T₂ between adjacent two of the trenches not sandwiching one of the plurality of first opening portion.

11. The semiconductor device according to claim 7, wherein each of the plurality of trenches is arranged substantially at a same distance from each of the plurality of first opening portions, the same distance being set at a minimum accessible value of distance between each of the trenches and the adjacent one of the contact regions.

12. The semiconductor device according to claim 7, wherein the drain layer is formed of the first conductivity type semiconductor, thereby forming a MOSFET.

13. The semiconductor device according to claim 7, wherein the drain layer is formed of the second conductivity type semiconductor, thereby forming one of an IGBT and an IEGT.

14. A semiconductor device comprising:

a first conductivity type high-resistance layer;

a second conductivity type base layer formed on the first conductivity type high resistance layer;

a plurality of the first conductivity type source layers formed in stripes in a surface of the second conductivity type base layer, each of the first conductivity type source layers having a plurality of first opening portions arranged staggeringly in two rows in parallel to the stripes so as to expose the second conductivity type base layer;

a plurality of trenches formed between adjacent two of the plurality of first conductivity type source layers, as viewed from above, and passing through the first conductivity type source layers and the second conductivity type base layer and extending to the first conductivity type high-resistance layer, in a depth direction;

a plurality of gate electrodes each being buried in a corresponding one of the plurality of trenches with a gate insulating film interposed therebetween;

an interlayer insulating film formed on the first conductivity type source layer having a plurality of second opening portions, each of the plurality of second opening portions exposing a first opening portion in which the second conductivity type base layer is exposed, and a region formed of said first conductivity type source layer surrounding the first opening portion;

a source electrode formed on the interlayer insulating layer, the source electrode being in contact with the plurality of second conductivity type base layers and the plurality of first conductivity type source layers through the plurality of second opening portions;

a drain layer formed on an opposite surface to a surface of the first conductivity type high-resistance layer having the second conductivity type base layer formed thereon; and

a drain electrode formed on the drain layer;

wherein one of the plurality of trenches formed between adjacent two of the source layers has a portion interposed in adjacent two of the first opening portions arranged in one of the two rows.

15. The semiconductor device according to claim 14, wherein each of the plurality of trenches is arranged substantially at a same distance from each of the plurality of first opening portions, the same distance being set at a minimum accessible value of distance between each of the trenches and adjacent one of the first opening portions.

16. The semiconductor device according to claim 14, wherein the drain layer is formed of the first conductivity type semiconductor, thereby forming a MOSFET.

17. The semiconductor device according to claim 14, wherein the drain layer is formed of the second conductivity type semiconductor, thereby forming one of an IGBT and an IEGT.