Ball grid array package

• US 6,060,778 A
• Filed: 04/15/1998
• Issued: 05/09/2000
• Est. Priority Date: 05/17/1997
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Jeong, Tae Sung, Lee, Tae Keun, Choi, Keun Hyoung, Ryu, Ki Tae, Youn, Han Shin, Park, Jum Sook
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US09/060,981
• Time in Patent Office: 755 Days
• Field of Search: 257/710, 257/693, 257/698, 257/700, 257/701-703, 257/706-708, 257/787, 257/783
• US Class Current: 257/710
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Disclosed is a packaged integrated circuit device with high heat dissipation performance and low weight. The packaged integrated circuit device includes an interconnection substrate having at least one layer of conductive trace material and at least one layer of insulating material and also having a first surface and a second surface disposed opposite to the first surface and having a plurality of electrical contacts formed on the second surface. At least one metal thermal conductive layer having a first surface is attached on the first surface of the interconnection substrate and having a second surface exposed to an exterior. A through hole region is formed in the interconnection substrate and the thermal conductive layer. An integrated circuit chip having a first surface exposed to an exterior and having also a second surface with a plurality of bond pads, opposite to the first surface of the integrated circuit chip, is placed within the through hole region. A plurality of bond wires make an electrical connection of the bond pads with the conductive trace layers. The bond wires and the integrated circuit chip are enclosed with an insulating encapsulant material. The through hole region is also filled with the insulating encapsulant material.

Claims

1. A packaged integrated circuit device, comprising:

an interconnection substrate having at least one conductive trace layer and at least one insulating layer and also having a first surface and a second surface having a plurality of electrical contacts thereon, opposite to the first surface of the interconnection substrate;

a dielectric layer attached to an outer portion of the first surface of the interconnection substrate;

a metal thermal conductive layer having a first surface and a second surface opposite to the first surface thereof, the first surface of the metal thermal conductive layer being attached to an internal portion of the first surface of the interconnection substrate and also being in contact with the internal end portion of the dielectric layer;

a hole region which is formed at the central portion of the interconnection substrate and which exposes the first surface of the metal thermal conductive layer;

an integrated circuit chip disposed within the hole region, the integrated circuit chip having a first surface attached the first surface of the interconnection substrate and a second surface opposite to the first surface of the integrated circuit chip, the second surface of the integrated circuit chip having a plurality of bonding pads formed thereon;

a plurality of bond wires for electrically connecting the bond pads with the conductive trace layer; and

an encapsulant material enclosing bond wires and the integrated circuit chip, the hole region being filled with the encapsulant material.

2. The packaged integrated circuit device of claim 1, wherein, the integrated circuit chip is aligned and held within the hole region by a sucking force of vacuum acting on the first surface thereof, and the plurality of bond pads on the integrated circuit chip and the conductive trace layer are electrically connected to each other by the plurality of bond wires in a condition where the sucking force acts.

3. The packaged integrated circuit device of claim 1, wherein the thermal conductive foil is made of a material selected from the group consisting of copper, aluminum, and silver.

4. The packaged integrated circuit device of claim 1, wherein the conductive trace layer is made of copper.

5. The packaged integrated circuit device of claim 1, the hole region has a circular cross sectional shape and includes at least one ear portion of a circular shape.

6. The packaged integrated circuit device of claim 1, wherein the plurality of electrical contacts are solder balls.

7. The packaged integrated circuit device of claim 1, wherein the integrated circuit chip is attached to the metal thermal conductive metal layer by an adhesive material containing silver.

8. The packaged integrated circuit device of claim 1, wherein the dielectric layer is made of a material selected from a group consisting of solder resist, polyimide, and epoxy.