Instantaneous junction temperature detection

• US 6,060,792 A
• Filed: 05/18/1998
• Issued: 05/09/2000
• Est. Priority Date: 05/20/1997
• Status: Expired due to Fees

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Pelly, Brian R.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Zura, Peter
• Application Number:
  US09/080,600
• Time in Patent Office: 722 Days
• Field of Search: 307/112, 307/116, 307/117, 307/125, 307/130, 307/131, 307/139, 361/18, 361/88, 361/91, 361/89, 361/93, 361/94, 361/98, 323/265, 323/271, 323/276
• US Class Current: 307/117
• CPC Class Codes: H03K 17/0828 in composite switches
• CPC Class Codes: H03K 2017/0806 against excessive temperature

Abstract

A circuit, for detecting a junction temperature of an insulated gate bipolar transistor (IGBT) which is alternately biased on and off in response to a gate signal, includes a differentiator circuit operable to receive a collector to emitter voltage of the IGBT and produce an output voltage proportional to a rate at which the collector to emitter voltage changes; and a feedback circuit operable to receive the output voltage and alter the gate signal when the output voltage indicates that the rate at which the collector to emitter voltage changes is outside a predetermined limit.

Claims

1. A circuit for detecting a junction temperature of an insulated gate bipolar transistor (IGBT), the IGBT being alternately biased on and off in response to a gate signal to control an amount of output current, the circuit comprising:

a differentiator circuit operable to receive a collector to emitter voltage of the IGBT and produce an output voltage proportional to a rate at which the collector to emitter voltage changes; and

a feedback circuit operable to receive the output voltage and alter the gate signal when the output voltage indicates that the rate at which the collector to emitter voltage changes is outside a predetermined limit.

2. The circuit of claim 1, wherein the feedback circuit alters the gate signal such that the average amount of output current is reduced when the output voltage indicates that the rate at which the collector to emitter voltage changes is outside the predetermined limit.

3. The circuit of claim 1, wherein the rate at which the collector to emitter voltage changes when the IGBT is biased off reduces in proportion to an increase in the junction temperature.

4. The circuit of claim 3, wherein the feedback circuit alters the gate signal when the output voltage indicates that the rate at which the collector to emitter voltage changes has fallen below a predetermined value.

5. The circuit of claim 4, wherein the predetermined value is a function of a type of IGBT to be utilized.

6. The circuit of claim 1, further comprising a enabling circuit operable to permit the feedback circuit to receive the output voltage from the differentiator circuit only during predetermined times.

7. The circuit of claim 6, wherein the predetermined times are when the IGBT is biased off.

8. The circuit of claim 7, wherein the enabling circuit includes:

an access circuit operable to permit the feedback circuit to receive the output voltage from the differentiator circuit in response to a window signal; and

a window circuit operable to produce the window signal when the IGBT has been biased off.

9. The circuit of claim 8, wherein the window circuit receives the gate signal and produces the window signal in the form of a pulse having a predetermined duration, the pulse initiating when the gate signal biases the IGBT off.

10. The circuit of claim 6, wherein the feedback circuit includes a sample and hold circuit operable to receive the output voltage from the enabling circuit during the predetermined times such that a sampled voltage representative of the output voltage at one of the predetermined times is available in the feedback circuit at times other than that predetermined time.

11. A circuit for detecting junction temperatures of at least first and second insulated gate bipolar transistors (IGBTs) of at least one half bridge circuit, the IGBTs being alternately biased on and off in response to first and second gate signals, respectively, to produce an output current, the circuit comprising:

a differentiator circuit operable to receive an input voltage from a node connecting an emitter of the first IGBT and a collector of the second IGBT, the differentiator circuit producing an output voltage proportional to a rate at which the input voltage changes; and

a feedback circuit operable to receive the output voltage and alter the first and second gate signals when the output voltage indicates that the rate at which the input voltage changes is outside predetermined limits.

12. The circuit of claim 11, wherein the feedback circuit alters the first and second gate signals such that the average output current is reduced when the output voltage indicates that the rate at which the input voltage changes is outside the predetermined limits.

13. The circuit of claim 11, wherein the rate at which the input voltage changes when the first or second IGBT is biased off reduces in proportion to an increase in junction temperature.

14. The circuit of claim 13, wherein

the output voltage includes a first part having a negative sense indicative of a negatively going rate caused by the first IGBT being biased off and a second part having a positive sense indicative of a positively going rate caused by the second IGBT being biased off, and

the feedback circuit altering the first and second gate signals when the output voltage indicates that the positively going or negatively going rate at which the input voltage changes has fallen below a predetermined value.

15. The circuit of claim 14, further comprising an absolute value circuit operable to receive the output voltage from the differentiator circuit and produce a rectified output voltage where the negative sense of the first part is made positive.

16. The circuit of claim 15, further comprising a enabling circuit operable to permit the feedback circuit to receive the rectified output voltage from the absolute value circuit only when the first or second IGBT is biased off.

17. The circuit of claim 16, wherein the enabling circuit includes:

an access circuit operable to permit the feedback circuit to receive the rectified output voltage from the absolute value circuit in response to a window signal; and

a window circuit operable to produce the window signal when at least one of the first and second IGBTs has been biased off.

18. The circuit of claim 17, wherein the window circuit receives the first and second gate signals and produces the window signal in the form of a pulse having a predetermined duration, the pulse initiating when at least one of the first and second gate signals bias a respective IGBT off.

19. The circuit of claim 16, wherein the feedback circuit includes a sample and hold circuit operable to receive the output voltage from the enabling circuit during the predetermined times such that a sampled voltage representative of the rectified output voltage at one of the predetermined times is available in the feedback circuit at times other than that predetermined time.