Lead-frame based vertical interconnect package

• US 6,061,251 A
• Filed: 09/08/1997
• Issued: 05/09/2000
• Est. Priority Date: 09/08/1997
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Walters, Peter, Hutchison, Brian R.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): FOSTER, DAVID A
• Application Number:
  US08/925,423
• Time in Patent Office: 974 Days
• Field of Search: 361/820, 361/816, 361/818, 361/800, 361/803, 361/792, 361/761, 361/762, 361/764, 361/767, 361/772, 174/35 R, 174/52.1, 174/250, 174/255, 257/734, 257/735, 257/736, 257/750, 257/774, 257/782, 257/784
• US Class Current: 361/820
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1627 stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A vertical interconnect package for electronic components and a method to manufacture same.

The invention provides a tripartite lead frame-based Vertical Interconnect Package (VIP) which provides integrated feedthrough and integrated shielding in a non-ceramic package. One frame functions as the substrate for coupling the IC device, the second lead frame and third lead frames form shielding and feedthroughs, with the third also providing a lid whereby an airtight chamber around the IC is formed. The invention provides a ground button (the shortest path to the die) divided into n sections providing additional RF and separate ground paths; lead frame connections are used for DC. A method for assembling includes batch lead frame assembly and test prior to singulation.

The VIP provides improved performance at lower manufacturing cost and provides easy interfaces to the printed circuit board in surface mount technology manufacturing and is compatible with die mount technologies such as flip-chip.

Claims

1. A package for a semiconductor device comprising:

a first conductive lead frame having a top and bottom side and at least a first and second lead,

a second conductive lead frame having a top and bottom, connected on the bottom to said first lead frame and forming a raised structure upon the first lead frame;

a semiconductor device being mounted on the top surface of the first conductive lead frame and being coupled to the first and second leads;

a third lead frame attached to the top of the second lead frame and not contacting the semiconductor device and providing a lidded chamber therefor.

5. A package as in claim 1 wherein the electronic device operates at a frequency at or above 50 GHz.

6. An interconnect as in claim 1 wherein the bond wires to the semiconductor device have a reduced arc, thereby providing connections with reduced loss, thermal resistance and ground.

2. A package for a semiconductor device comprising:

a first conductive lead frame having a top and bottom side and at least a first and second lead,

a second conductive lead frame having a top and bottom, connected on the bottom to said first lead frame and forming a raised structure upon the first lead frame; and

said first and second lead frames being encapsulated in plastic, said encapsulation exclusive of the bonding and soldering surfaces said bonding and soldering surfaces being plated;

a semiconductor device being mounted on the top surface of the first conductive lead frame and being coupled to the first and second leads;

a third lead frame formed so as to create a lidded chamber in which the semiconductor device is mounted, said third lead frame attached to the top of the second lead frame and said lid not contacting the semiconductor device.

3. The semiconductor package as in claim 2 wherein the first lead frame includes at least one ground pad, at least one RF and DC ports.

4. An electrically conductive semiconductor device interconnect providing integrated feedthrough and integrated shielding comprising a first, second and third lead frame each having an upper and a lower surface;

the first frame having two or more ground pads, and at least one RF port;

the second lead frame being attached to the upper side first and plastic encapsulating the frame elements of the first lead frame excepting the upper surface to which the semiconductor device is attached, coupled to the grounds, and the lower surface;

said second lead frame attached to said first lead frame and providing a raised structure around said semiconductor device;

said third lead frame attached to said second lead frame, not contacting the semiconductor device, and forming a lidded chambers said lidded chamber containing said semiconductor device.

7. A package for an electronic device comprising:

a first conductive substrate;

nonconductive packaging material surrounding a predetermined portion of the conductive substrate, the electronic device coupled to the conductive substrate in an area devoid of packaging material;

an intermediate conductive substrate coupled to the first conductive substrate and which provides a raised structure around the electronic device;

a third conductive substrate attached to the intermediate substrate forming a sealed lidded chamber around the electronic device and not in physical contact with the electronic device.

8. A package as in claim 7 wherein n (n is greater than 2) conductive substrates are coupled and wherein a plurality of electronic devices are attached to one or more of n conductive substrates.

9. A method for fabricating a high performance integrated circuit package with increased package level shielding and increased isolation performance, the method comprising the steps of:

forming a conductive lead frame having an upper and lower surface and at least a first and second lead;

forming a second lead frame having an upper and a lower surface;

attaching said second lead frame to the upper surface of the first lead frame, the second lead frame forming a raised structure around the first lead frame and leaving the lower surface of the first lead frame exposed;

encapsulating the first and second lead frames in plastic, excepting the surfaces intended for soldering or plating;

deflashing the unencapsulated surfaces;

plating all exposed metal surfaces;

attaching semiconductor device to upper exposed surface of first lead frame;

forming a third lead frame and plating said third lead frame;

attaching said third lead frame to the upper surface of the second lead frame, said third lead frame not contacting the semiconductor device and forming a lidded chamber having a sealed air pocket over said semiconductor device.

10. A method for fabricating a package for an electronic device, wherein said package provides integrated feedthroughs and shielding by means of first, second, and third leadframe structures, said method comprising the steps of:

attaching to the first lead frame the electronic device;

attaching the second lead frame to the first lead frame, forming necessary couplings for all feedthrough connections;

attaching the third lead frame to the second lead frame to form a lidded chamber, thereby sealing the package.

11. A method as in claim 10 further comprising the steps of attaching more than one IC per package and testing the batch lead frame prior to singulation.

12. A method as in claim 10 further including the step of encapsulating predetermined portions of the first lead frame in plastic prior to attaching the second lead frame.

13. A method as in claim 10 further including the steps of selectively modifying the thickness of various portions of the first, second and third lead frame.