Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices

• US 6,061,296 A
• Filed: 08/17/1998
• Issued: 05/09/2000
• Est. Priority Date: 08/17/1998
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Stephens, Michael C. Jr., Ternullo, Luigi Jr., Ematrudo, Christopher
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/135,252
• Time in Patent Office: 631 Days
• Field of Search: 365/233, 365/202, 365/194, 365/190, 365/208
• US Class Current: 365/233.11
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

Claims

1. A method for accessing data in a memory array, the method comprising:

sensing a bit in the memory array;

generating a first clock signal, the first clock signal having a first pulse;

generating a second clock signal, the second clock signal having a second pulse;

generating a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse; and

propagating a signal representing a logic level of the bit to an output line through a plurality of stages, the plurality of stages including a first stage and a second stage, the first stage being coupled to a first interconnect and a second interconnect, the second stage being coupled to the second interconnect and the output line, wherein;

the first interconnect is configured to receive a first data signal that is dependent on the logic level of the bit;

the second pulse causes the first stage to generate on the second interconnect a second data signal as a function of the first data signal; and

the third pulse causes the second stage to generate onto the output line an output signal that is dependent on the second data signal, and

wherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.

2. The method of claim 1 wherein during the first mode, the second pulse occurs in a first cycle and the third pulse occurs in a next cycle.

3. The method of claim 1 wherein during the second mode, the second and fourth pulses begin in a first cycle and the third pulse begins in a next cycle.

4. The method of claim 1 wherein the first pulse causes a restore operation of the first interconnect.

5. The method of claim 4 wherein the second pulse causes a restore operation of the second interconnect.

6. The method of claim 1 wherein the plurality of stages consists of four stages.

7. The method of claim 1 wherein the third clock signal is generated in response to a delayed version of an external clock signal, the delayed external clock signal also triggering an output enable signal.

8. The method of claim 7 wherein the timing of the third clock signal is programmable while maintaining an essentially constant relative timing between the output enable signal and the third clock signal.

9. The method of claim 1 wherein the timing of the third clock signal is programmable while maintaining an essentially constant relative timing between the second clock signal and the third clock signal during the second mode.

10. The method of claim 9 further comprising selectively causing pulses of the first clock signal or the third clock signal to trigger pulses in the second clock signal.

11. A circuit for accessing data in a memory array, the circuit comprising:

means for sensing a bit in the memory array;

a plurality of stages including a first stage and a second stage;

a first interconnect coupled to the first stage configured to receive a first data signal that is dependent on the logic level of the bit;

a second interconnect configured to couple the first stage to the second stage;

an output line coupled to the second stage;

means for generating a first clock signal, the first clock signal having a first pulse;

means for generating a second clock signal, the second clock signal having a second pulse, wherein the second pulse causes the first stage to generate on the second interconnect a second data signal as a function of the first data signal; and

means for generating a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse, wherein the third pulse causes the second stage to generate onto the output line an output signal that is dependent on the second data signal;

wherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.

12. The circuit of claim 11 wherein during the first mode, the second pulse begins in a first cycle and the third pulse begins in a next cycle.

13. The circuit of claim 11 wherein during the second mode, the second and fourth pulses begin in a first cycle and the third pulse begins in a next cycle.

14. The circuit of claim 11 wherein the first pulse causes a restore operation of the first interconnect.

15. The circuit of claim 14 wherein the second pulse causes a restore operation of the second interconnect.

16. The circuit of claim 11 wherein the plurality of stages consists of four stages.

17. The circuit of claim 11 further comprising means for generating an output enable signal, wherein a pulse of the output enable signal is triggered by a pulse of a delayed version of an external clock signal.

18. The circuit of claim 17 further comprising a programmable delay for selectively adjusting the timing of the third clock signal while maintaining an essentially constant relative timing between the output enable signal and the third clock signal.

19. The circuit of claim 11 further comprising means for selectively adjusting the timing of the third clock signal while maintaining an essentially constant relative timing between the second clock signal and the third clock signal during the second mode.

20. The circuit of claim 19 further comprising means for selectively causing pulses of the first clock signal or the third clock signal to trigger pulses in the second clock signal.

21. A circuit for accessing data in a memory array, the circuit comprising:

a timing circuit configured to provide;

a first clock signal, the first clock signal having a first pulse;

a second clock signal, the second clock signal having a second pulse; and

a third clock signal, the third clock signal having a third pulse and a fourth pulse, the fourth pulse occurring before the third pulse;

a first sense amplifier coupled to the memory array, wherein the first sense amplifier is configured to sense a bit in the memory array;

a first interconnect coupled to the first sense amplifier, wherein the first interconnect is configured to receive a first data signal that is dependent from the bit;

a second sense amplifier coupled to the first interconnect, wherein, in response to the second pulse, the second sense amplifier is configured to generate a second data signal as a function of the first data signal;

a second interconnect coupled to receive the second data signal; and

a third sense amplifier coupled to the second interconnect, wherein, in response to the third pulse, the third sense amplifier is configured to output onto an output line an output data signal as a function of the second data signal;

wherein, during a first mode, the second pulse is triggered by the first pulse and, during a second mode, the second pulse is triggered by the fourth pulse.

22. The circuit of claim 21 further comprising:

a third interconnect coupled to the first sense amplifier; and

a fourth sense amplifier coupled between the first interconnect and the third interconnect, wherein, in response to the first pulse, the fourth sense amplifier is configured to generate the first data signal.

23. The circuit of claim 21 wherein during the first mode, the second pulse begins in a first cycle and the third pulse begins in a next cycle.

24. The circuit of claim 21 wherein during the second mode, the second and fourth pulses begin in a first cycle and the third pulse begins in a next cycle.

25. The circuit of claim 21 wherein the first pulse causes a restore operation of the first interconnect.

26. The circuit of claim 25 wherein the second pulse causes a restore operation of the second interconnect.

27. The circuit of claim 21 further comprising an output enable buffer, wherein the output enable buffer is configured to generate an output enable signal having pulses triggered by pulses of a delayed version of an external clock signal.

28. The circuit of claim 27 further comprising a programmable delay circuit, the programmable delay circuit being configured to generate the delayed version of the external clock signal, wherein the programmable delay circuit is configurable to adjust the delay of the delayed version of the external clock signal.

29. The circuit of claim 28 wherein the programmable delay circuit is configurable to adjust the timing of the third clock signal while maintaining an essentially constant relative timing between the output enable signal and the third clock signal.

30. The circuit of claim 21 further comprising a programmable timing circuit, wherein the programmable timing circuit is configurable to adjust the timing of the third clock signal while maintaining an essentially constant relative timing between the second clock signal and the third clock signal during the second mode.

31. The circuit of claim 30 wherein the programmable timing circuit is further configured to cause the first clock signal to trigger pulses in the second clock signal during the first mode and to cause the third clock signal to trigger pulses in the second clock signal during the second mode.