Reconstruction engine for a hardware circuit emulator

• US 6,061,511 A
• Filed: 06/12/1998
• Issued: 05/09/2000
• Est. Priority Date: 06/12/1998
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: IKOS Systems Incorporated (Siemens AG)
• Inventors: Stewart, William K., Selvidge, Charley, Marantz, Joshua D., Kudlugi, Muralidhar R., Seneski, Mark E., Crouch, Ken
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Broda, Samuel
• Application Number:
  US09/097,138
• Time in Patent Office: 697 Days
• Field of Search: 395/500, 395/500.45, 395/500.46, 395/500.47, 395/500.48, 395/500.49, 714/47
• US Class Current: 703/28
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input signals and memory output signals ("sample signals") are saved by a logic analyzer, and used in an emulator to generate state vectors from a state snapshot previously recorded. Data compression techniques can be applied to minimize storage requirements, and parallel evaluation of segments of waveforms can be achieved, since saved states for the entire period of interest are available for waveform reconstruction at the time of the logic evaluation.

Claims

1. A method for providing visibility into state nets of a design under emulation, comprising:

running said emulation for said design in an emulator and, during emulation, (a) providing at predetermined intervals snapshots of said emulation, each snapshot including output values of state elements of said design; and

(b) providing at each transition of a clock signal within said design, a set of sample signals, each set of sample signals including primary input signals of said design and output values of memory circuits of said design;

at a subsequent time, re-running said emulation by loading into an emulator the values of said state elements using a selected one of said snapshots and, at each clock transition subsequent to said snapshot, (a) applying said sample signals corresponding to said clock transition to said design, and (b) providing as output a state vector corresponding to said clock signal transition, said state vector including values of said state elements at said clock signal transition; and

receiving said state vectors and said sample signals into a reconstruction engine, and evaluating waveforms of said nets of said design using said state vectors and said sample signals.

2. A method as in claim 1, wherein said predetermined intervals are computed from the number of transitions in multiple clock domains.

3. A method as in claim 1, wherein said sample signals are recorded by a logic analyzer.

4. A method as in claim 1, wherein said sample signals further comprises logic signals from combinational circuits that include cycles.

5. A method as in claim 4, wherein said logic signals are provided as sample signals back into said combinational circuits during said re-running of said emulation.

6. A method as in claim 1, wherein said emulation is run using a virtual clock signal, wherein the number of cycles of said virtual clock signal between successive sets of said sample signals are recorded, and wherein when said re-running step applies to said design said sets of sample signals, said re-running step maintains said number of cycles of said virtual clock between application.

7. A method as in claim 1, further comprising storing said snapshots in first-in-first-out (FIFO) memories associated with said state elements.

8. A method as in claim 1, wherein said state vectors are stored using a data compression technique.

9. A method as in claim 8, wherein said data compression technique comprises run-length encoding.

10. A method as in claim 1, wherein said emulation replaces latches in said design by flip-flops having timing characteristic different from timing characteristics of said latches, wherein said evaluation step restores to said design said timing characteristics of said latches.

11. A method as in claim 1, further comprising viewing said waveforms with a waveform tool.

12. A method as in claim 1, wherein said step of evaluating waveforms of said nets performs evaluation of multiple segments of a waveform in parallel.

13. A method as in claim 1, said sample signals are applied to said design under said modeling process through a scan chain circuit generated for said design.

14. A method as in claim 1, said state vector is provided from said design under said emulation through a scan chain circuit generated for said design.

15. A method as in claim 1, wherein said evaluation step being performed using a reconstruction model generated from said design under emulation.

16. A method as in claim 15, further comprising generating said reconstruction model from said design, said reconstruction model comprising source models which can be compiled into executable object code.

17. A method as in claim 16, further comprising a partially elaborating of a hierarchy of said design prior to generating said reconstruction model.

18. A method as in claim 15, wherein said reconstruction model includes both a net list of design and utility routines callable from said reconstruction engine to perform said evaluation step.

19. A system for reconstructing waveforms of state nets of a design under emulation in an emulator, comprising:

a model compiler compiling said design into a logic circuit configurable in said emulator, said model compiler providing, for selected state elements, a memory circuit for saving a value of each of said state elements, and a loading circuit for loading a value into each of said state elements;

an emulation controller receiving from said model compiler said logic circuit, said emulation controller causing (a) a first emulation of said logic circuit, (b) snapshots of said selected state elements in said logic circuit to be saved into said memory circuit at predetermined intervals, each snapshot including values of state elements in said logic circuit, and (c) at a later time, a second emulation of said logic circuit starting from one of said snapshots of said selected state elements and providing from said second emulation state vectors at selected times, each said state vectors including values of said selected state elements at the corresponding one of said selected times; and

an interface to a reconstruction engine, said interface providing to said reconstruction engine a representation of said design and said state vectors for use in an evaluation of said logic circuit to obtain said waveforms.

20. A system as in claim 19, wherein said memory circuit comprises a first-in-first-out (FIFO) memory.

21. A system as in claim 19, further comprising a logic analyzer coupled to said emulator, said model compiler further providing a probe circuit in said logic circuit for routing primary input signals to said logic analyzer.

22. A system as in claim 21 wherein said probe circuit further provides said logic analyzer output signals of memory elements in said logic circuit.

23. A system as in claim 22, wherein said interface to said reconstruction engine provides said sample signals to said logic evaluation, said sample signals including said output signals of said memory elements and said primary input signals.

24. A system as in claim 23, wherein said sample signals further comprising signals from a combinational logic circuit that includes a cycle.

25. A system as in claim 19, wherein said representation of said design includes an executable model of said design and utility routines for data management and for application of said state vectors to said executable model.

26. A system as in claim 25, further comprising a second model compiler for generating said executable model, said second model compiler comprising a partial circuit elaborater for providing a partially elaborated executable model of said design.

27. A system as in claim 25, wherein said reconstruction model includes utility routines for performing reconstruction of multiple portions of one of said waveforms in parallel.

28. A system as in claim 19, wherein said model compiler further provides in said logic circuit a scan chain for providing said values into said loading circuit and for retrieving said state vectors from said selected state elements.

29. A system as in claim 19, wherein said model compiler replaces latches in said design by flip-flops, said flip-flops having timing characteristics different from the timing characteristics of said latches, wherein said logic evaluation restores to said design the timing characteristics of said latches.

30. A system as in claim 19, further comprising a storage element receiving for storage said state vectors, said storage element storing said state vectors using a data compression technique.

31. A system as in claim 30, wherein said data compression technique comprises run-length encoding of a repetitious pattern.

32. A method for reconstructing a waveform of an internal terminal of a circuit over a given time period, said circuit having one or more clock domains, said method comprising:

synchronizing each of said clock domains to a virtual clock domain of higher frequency than the frequency of each of said clock domains;

using a counter, maintaining an index of the clock periods of said virtual clock domain;

receiving logic values of state elements of said circuit at successive clock transitions of said clock domains over said time period, and keeping track of successive clock transitions by storing the values of said index when said successive clock transitions occur;

receiving input values to said circuit at said successive clock transitions of said clock domains; and

evaluating said waveform using a model of said circuit, and applying said logic values of said state elements, and said input values to said circuit, using said stored values of said index to maintain relative times of occurrence of said successive clock transitions.

33. A method as in claim 32, wherein said evaluating step evaluates selected time points on said waveform in parallel.

34. A method as in claim 32, wherein said logic values of state elements being received from a modeling process.

35. A method as in claim 34, wherein said modeling process comprises an emulation in an emulator.

36. A method as in claim 34, wherein said modeling process comprises a simulation in a logic simulator.

37. A method as in claim 32, further comprising the step of receiving a logic value from each combinational cycle of said circuit at successive clock transitions of said clock domains over said time period.

38. A method as in claim 32, further comprising the step of viewing said waveform in a waveform viewer.

39. A method as in claim 38, wherein said waveform is selected through a user interface, and said evaluation step being carried out upon selection of said waveform.

40. A method as in claim 32, wherein said logic values and said input values are stored using data compression techniques.

41. A method as in claim 32, wherein said model of said circuit is provided as executable code.