Efficient context saving and restoring in a multi-tasking computing system environment

• US 6,061,711 A
• Filed: 08/19/1996
• Issued: 05/09/2000
• Est. Priority Date: 08/19/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Song, Seungyoon Peter, Mohamed, Moataz A., Raffman, Andrew R., Van Aken, Jerry R., Nguyen, Le T., Forin, Alessandro, Park, Heonchul
• Primary Examiner(s): Banankhah, Majid A.
• Assistant Examiner(s): LAO, SUE X
• Application Number:
  US08/699,280
• Time in Patent Office: 1,359 Days
• Field of Search: 395/650, 395/678, 395/677, 395/569, 395/591, 709/108, 709/107, 712/228, 712/244
• US Class Current: 718/108
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program. Unnecessarily saving and loading all available processor state information can be noticeably inefficient particularly where relatively large amounts of processor state information exists. In one embodiment, a processor requests a co-processor to context switch out the currently executing program. At a predetermined appropriate point in the executing program, the co-processor responds by halting program execution and saving only the minimal amount of processor state information necessary for successful restoration of the program. The appropriate point is chosen by the application programmer at a location in the executing program that requires preserving a minimal portion of the processor information across a context switch. By saving only a minimal amount of processor information, processor time savings are accumulated across context save and restoration operations.

Claims

1. A process comprising:

executing a first program on a first processor;

receiving a context switch request from a second processor;

responding to the context switch request at an appropriate point in the first program, the appropriate point being one of a plurality of predetermined points indicated by a plurality of markers in the first program, the plurality of predetermined points including selected predetermined points located at a proximate point in the first program that is predetermined to be a point in which the first processor requires a minimal amount of processor state information storage for successful restoration of the first program;

continuing to execute the first program after receiving the context switch request;

wherein the responding comprises;

encountering the marker in the first program at the appropriate point;

interrupting the first processor;

reading the context switch request with the first processor in response to encountering the marker in the first program;

storing a return address of the first program;

storing the minimal amount of processor state information required for successful restoration of the first program; and

notifying the second processor of the availability of the first processor to execute a second program.

2. A process as in claim 1 further comprising:

interspersing a plurality of markers in the first program at locations requiring a minimal amount of processor state information storage for successful restoration of the first program.

3. A process as in claim 1 further comprising:

saving the processor state information corresponding to a state of the first program at the appropriate point;

switching out the first program;

executing a second program on the first processor;

switching out the second program; and

restoring the first program using the minimal amount of stored process information.

4. A process as in claim 1 wherein the responding comprises:

saving the processor state information corresponding to a state of the first program at the appropriate point; and

saving the location of a context restoration routine for seamlessly restoring the first program.

5. A process as in claim 1 wherein the executing step comprises:

executing the first program on a vector processor of a multi-media signal processor in a multimedia multiprocessor system.

6. A process as in claim 1 further comprising:

receiving data from a plurality of multi-media devices; and

wherein the executing comprises;

processing the received data.

7. A process as in claim 1 wherein the receiving comprises:

reading a register having a context switch enable field set by the second processor.

8. A process as in claim 1 wherein the marker is a conditional context switch instruction.

23. A process as in claim 1 wherein the proximate point in the first program is a point in the first program so that noticeable delays are avoided between the receiving a context switch request and responding to the context switch request.

9. A computing system comprising:

a first processor in a multi-tasking environment for executing programs having respective pluralities of interspersed context switch markers, the pluralities of interspersed context switch markers being located in the programs at predetermined points, the predetermined points including points determined to be proximate to locations in which the first processor requires a minimal amount of processor state information storage for successful restoration of the programs;

a first memory, coupled to the first processor, allocated to storage of processor state information;

a second memory coupled to the first processor;

a context switch request detector operating on the first processor for detecting, after the processor encounters one of the markers in an executing program, a request to context switch out the program; and

a context saving module operating on the first processor for responding to a detected context switch request by saving in the second memory processor state information located in the first memory, wherein the contest saving module includes;

a module being operable to encounter the marker in the first program at the appropriate point;

a module operable to interrupt the first processor;

a module operable to read the context switch request with the first processor in response to encountering the marker in the first program;

a module operable to store a return address of the first program;

a module operable to store the minimal amount of processor state information required for successful restoration of the first program; and

a module operable to notify the second processor of the availability of the first processor to execute a second program.

10. A computing system as in claim 9 wherein the context saving module further responds to the detected context switch by saving a location of a context restoration module.

11. A computing system as in claim 9 further comprising:

a second processor mutually coupled to the first processor, the first and second processors having asymmetric characteristics, the second processor including a mechanism for requesting the first processor to context switch out an executing program.

12. A computing system as in claim 11 further comprising:

an interface unit coupled between the first and second processors, the interface unit including a register mutually accessible by the first and second processors;

wherein the second processor is capable of writing to the register to indicate a context switch request; and

wherein the first processor is capable of reading the register to detect a context switch request from the second processor.

13. A computing system as in claim 11 wherein:

the second processor is a control processor; and

the first processor is a vector processor.

14. A computing system as in claim 9 further comprising:

a context restoring module operating on the first processor for restoring a context switched out program by returning to the first memory the saved processor state information located in the second memory associated with the context switched out program.

15. A computing system as in claim 9 wherein the markers are generally regularly interspersed throughout the program at locations which require a minimal of processor state information to successfully restore the program.

16. A computing system as in claim 9 wherein the markers are conditional context switch instructions.

17. An efficient context saving process in a multi-tasking, multiprocessor computing system environment, comprising:

inserting conditional context switch instructions into a first program at a plurality of predetermined points in the first program;

executing the first program;

receiving a context switch request;

detecting one of the conditional context switch instructions;

determining whether the context switch request exists from a first processor following the detecting one of the conditional context switch instructions; and

switching out the first program comprising;

saving a return address of the program upon determining the existence of a context switch request, otherwise continuing to execute the first program; and

executing a context saving module, comprising;

storing processor state information corresponding to a state of the first program prior to detecting the conditional context switch instruction;

saving a location of context restoration module;

interrupting the first processor,

continuing to execute the first program after receiving the context switch request;

wherein the first proven responds to the context switch, the responding comprises;

encountering the marker in the first program at the appropriate point;

interrupting the first processor;

reading the context switch request with the first processor in response to encountering the marker in the first program;

storing a return address of the first program;

storing the processor state information required for successful restoration of the first program; and

notifying a second processor of the availability of the first processor to execute a second program.

18. A process as in claim 17 further comprising:

switching in the program comprising;

executing a context restoration module, comprising;

loading the processor state information previously stored in the context saving module executing step; and

loading the saved return of the program previously saved in the program switching out step; and

executing the program.

19. A process as in claim 17 further comprising:

executing the program on a co-processor; and

submitting the context switch request from a control processor to an interface unit.

20. A process as in claim 17 wherein the inserting conditional context switch instructions into a program comprises:

inserting the conditional context switch instructions approximately regularly throughout the program so that the conditional context switch instructions are inserted at locations in the program that require a minimal amount of processor state information preservation in anticipation of context switching in the program.

21. A process as in claim 20 wherein the inserting further comprises:

inserting the conditional context switch instructions at approximately regular intervals so that noticeable delays are avoided between the steps of receiving the context switch request and detecting one of the conditional context switch instructions.

22. A process as in claim 17 wherein the executing a program comprises executing the program on a first processor, the process further comprising:

approximately regularly interrupting the first processor upon detecting one of the conditional context switch instructions.