Failover system for a DASD storage controller reconfiguring a first processor, a bridge, a second host adaptor, and a second device adaptor upon a second processor failure

• US 6,061,750 A
• Filed: 02/20/1998
• Issued: 05/09/2000
• Est. Priority Date: 02/20/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kalos, Matthew Joseph, Knowlden, Ronald Robert, Beardsley, Brent C.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Park, Ilwoo
• Application Number:
  US09/026,622
• Time in Patent Office: 809 Days
• Field of Search: 714/11, 714/3, 714/5, 714/8, 714/9, 714/10, 711/112, 711/113, 711/114, 710/8, 710/10, 710/17, 710/74
• US Class Current: 710/74
• CPC Class Codes: G06F 11/2092 Techniques of failing over between control units

Abstract

Disclosed is a storage controller for interfacing between a plurality of host systems and direct access storage devices (DASDs). The storage controller includes a bridge, a first host adaptor, and a first device adaptor that are configured to communicate with a first processor. A first DASD is linked to the first device adaptor. The bridge interfaces the first processor, the first host adaptor, and the first device adaptor. The storage controller further includes a second host adaptor and a second device adaptor that are configured to communicate with a second processor. A second DASD is linked to the second device adaptor. The bridge further interfaces the second processor, the second host adaptor, and the second device adaptor. After configuration, an input/output (I/O) request from at least one of the host systems is directed to the first DASD via the first host adaptor, the first processor, and the first device adaptor. An I/O request from at least one of the host systems to the second DASD is directed via the second host adaptor, the second processor, and the second device adaptor. Upon determining that the second processor has failed, the first processor configures the second host adaptor and second device adaptor to communicate with the first processor. After configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second DASD is transferred via the second host adaptor, the first processor, and the second device adaptor.

Claims

1. A method for a storage controller to interface between a plurality of host systems and direct access storage devices (DASDs), comprising the steps of:

(a) configuring a bridge, a first host adaptor, and a first device adaptor to communicate with a first processor, wherein a first DASD is linked to the first device adaptor, and wherein the bridge interfaces the first processor, the first host adaptor, and the first device adaptor;

(b) configuring the bridge, a second host adaptor, and a second device adaptor to communicate with a second processor, wherein a second DASD is linked to the second device adaptor, and wherein the bridge interfaces the second processor, the second host adaptor, and the second device adaptor;

(c) directing an input/output (I/O) request from at least one of the host systems to the first DASD via the first host adaptor, the first processor, and the first device adaptor;

(d) directing an I/O request from at least one of the host systems to the second DASD via the second host adaptor, the second processor, and the second device adaptor;

(e) determining whether the second processor has failed; and

(f) configuring, with the first processor, the bridge, the second host adaptor, and second device adaptor to communicate with the first processor, wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second DASD is transferred via the second host adaptor, the first processor, and the second device adaptor.

2. The method of claim 1, further comprising the step of configuring the bridge to block communication between the second processor and the bridge upon determining that the second processor has failed.

3. The method of claim 1, wherein the first and second device adaptors each include a non-volatile storage unit (NVS) and further including the steps of buffering data written to the first DASD in the NVS within the first device adaptor and buffering data written to the second DASD in the NVS within the second device adaptor.

4. The method of claim 1, further including the steps of:

determining with the first processor whether the first device adaptor has failed when at least one of the host systems directs a request toward the first DASD; and

generating a message to at least one of the host systems directing a request toward the first DASD to be communicated via the failed first device adaptor indicating that the first DASD is inaccessible after determining that the first device adaptor has failed.

5. The method of claim 1, wherein the bridge is comprised of a first bridge that provides communication between the host adaptors and the processors and a second bridge that provides communication between the processors and the device adaptors.

6. The method of claim 1, wherein the first DASD comprises a first group of at least one DASD and the second DASD comprises a second group of at least one DASD, further including the steps of:

mapping, with the first processor, data in the first group of DASDs to a format that at least one of the host systems interprets as a first logical unit number (LUN);

mapping, with the second processor, data in the second group of DASDs to a format that at least one of the host systems interprets as a second LUN;

directing data from at least one of the host systems to the first processor via the first host adaptor and the bridge, wherein the first processor maps the data routed thereto to an addressable area in the first group of DASDs;

directing data from at least one of the host systems to the second processor via the second host adaptor and the bridge, wherein the second processor maps the data routed thereto to an addressable area in the second group of DASDs, wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second group of DASDs is routed via the second host adaptor to the first processor, wherein the first processor maps the data routed to the second group of DASDs to the addressable area in the second group of DASDs.

7. A storage controller for interfacing between a plurality of host systems and direct access storage devices (DASDs), comprising:

(a) a first host adaptor;

(b) a first device adaptor;

(c) a first DASD linked to the first device adaptor;

(d) a first processor;

(e) a bridge, wherein the first processor, first host adaptor, and the first device adaptor interface via a bridge, wherein an input/output (I/O) request from at least one of the host systems is directed to the first DASD via the first host adaptor, the first processor, and the first device adaptor;

(f) a second host adaptor;

(g) a second device adaptor;

(h) a second DASD linked to the second device adaptor; and

(i) a second processor in communication with the second host adaptor and the second device adaptor via the bridge, wherein an input/output (I/O) request from at least one of the host systems is directed to the second DASD via the second host adaptor, the second processor, and the second device adaptor, wherein the first processor is capable of determining whether the second processor has failed, wherein, after determining that the second processor has failed, the first processor configures the bridge, the second host adaptor, and the second device adaptor to communicate with the first processor, and wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second DASD is transferred via the second host adaptor, the first processor, and the second device adaptor.

8. The storage controller of claim 7, wherein the bridge is further comprised of a first bridge that provides communication between the host adaptors and the processors and a second bridge that provides communication between the processors and the device adaptors.

9. The storage controller of claim 7, further including:

a non-volatile storage unit (NVS) in the first device adaptor, wherein the NVS buffers data written to the first DASD;

an NVS in the second device adaptor, wherein the NVS buffers data written to the second DASD.

10. A storage controller to interface between a plurality of host systems and direct access storage devices (DASDs), comprising:

(a) means, performed by a first processor, for configuring a first host adaptor and a first device adaptor to communicate with a first processor;

(b) means, performed by a second processor, for configuring a second host adaptor and a second device adaptor to communicate with a second processor;

(c) bridge means for interfacing the first processor, the first host adaptor, and the first device adaptor and for interfacing the second processor, the second host adaptor, and the second device adaptor;

(d) a first DASD linked to the first device adaptor, wherein an input/output (I/O) request from at least one of the host systems is directed to the first DASD via the first host adaptor, the first processor, and the first device adaptor;

(e) a second DASD linked to the second device adaptor, wherein an I/O request from at least one of the host systems is directed to the second DASD via the second host adaptor, the second processor, and the second device adaptor;

(f) means, performed by the first processor, for determining whether the second processor has failed; and

(g) means, performed by the first processor, for configuring the bridge means, the second host adaptor, and the second device adaptor to communicate with the first processor upon determining that the second processor has failed, wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second DASD is transferred via the second host adaptor, the first processor, and the second device adaptor.

11. The storage controller of claim 10, further comprising means, performed by the first processor, for configuring the bridge means to block communication between the second processor and the bridge upon determining that the second processor has failed.

12. The storage controller of claim 10, further including:

means, performed by the first processor, for determining whether the first device adaptor has failed when at least one of the host systems directs a request toward the first DASD; and

means for generating a message to at least one of the host systems directing a request toward the first DASD to be communicated via the failed first device adaptor indicating that the first DASD is inaccessible after determining that the first device adaptor has failed.

13. The storage controller of claim 10, wherein a host system is linked to the first host adaptor via a dual bus host, and further including:

means, performed by the host system, for determining whether the first host adaptor is inaccessible; and

means, performed by the host system, for directing the request to another host adaptor attached to the dual bus host upon determining that the first host adaptor is inaccessible.

14. The storage controller of claim 10, wherein the first DASD comprises a group of at least one DASD and the second DASD comprises a group of at least one DASD, further including:

means, performed by the first processor, for mapping data in the first group of DASDs to a format that at least one of the host systems interprets as first a logical unit number (LUN);

means, performed by the second processor, for mapping data in the second group of DASDs to a format that at least one of the host systems interprets as a second LUN;

means for directing data from at least one of the host systems to the first processor via the first host adaptor and the bridge means, wherein the first processor maps the data routed thereto to an addressable area in the first group of DASDs; and

means for directing data from at least one of the host systems to the second processor via the second host adaptor and bridge means, wherein the second processor maps the data routed thereto to an addressable area in the second group of DASDs, wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second group of DASDs is routed via the second host adaptor to the first processor, wherein the first processor maps the data directed to the second groups of DASDs to the addressable area in the second group of DASDs.

15. An article of manufacture for use in programming a storage controller to direct data between a plurality of host systems and direct access storage devices (DASDs), the article of manufacture comprising a storage medium having logic embodied therein that causes components of the storage controller to perform the steps of:

(a) configuring a bridge, a first host adaptor, and a first device adaptor to communicate with a first processor, wherein a first DASD is linked to the first device adaptor, and wherein the bridge provides communication among the first processor, the first host adaptor, and the first device adaptor;

(b) configuring the bridge, a second host adaptor, and a second device adaptor to communicate with a second processor, wherein a second DASD is linked to the second device adaptor, and wherein the bridge provides communication among the second processor, the second host adaptor, and the second device adaptor;

(c) directing an input/output (I/O) request from at least one of the host systems to the first DASD via the first host adaptor, the first processor, and the first device adaptor;

(d) directing an I/O request from at least one of the host systems to the second DASD via the second host adaptor, the second processor, and the second device adaptor;

(e) determining whether the second processor has failed; and

(f) configuring with the first processor the bridge, the second host adaptor, and the second device adaptor to communicate with the first processor in response to determining that the second processor has failed, wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second DASD is transferred via the second host adaptor, the first processor, and the second device adaptor.

16. The article of manufacture of claim 15, further causing the first processor to perform the step of configuring the bridge to block communication between the second processor and the bridge upon determining that the second processor has failed.

17. The article of manufacture of claim 15, wherein the first and second device adaptors each include a non-volatile storage unit (NVS) and further causing the storage controller to buffer data written to the first DASD in the NVS within the first device adaptor and buffer data written to the second DASD in the NVS within the second device adaptor.

18. The article of manufacture of claim 15, further causing the components of the storage controller to perform the steps of:

determining whether the first device adaptor has failed when at least one of the host systems directs a request toward the first DASD; and

generating a message to at least one of the host systems directing a request toward the first DASD to be communicated via the failed first device adaptor indicating that the first DASD is inaccessible after determining that the first device adaptor has failed.

19. The article of manufacture of claim 15, wherein the first DASD comprises a first group of at least one DASD and the second DASD comprises a second group of at least one DASD, further causing the components of the storage controller to perform the steps of:

mapping, with the first processor, data in the first group of DASDs to a format that the host system interprets as a first logical unit number (LUN);

mapping, with the second processor, data in the second group of DASDs to a format that the host system interprets as a second LUN;

directing data from at least one of the host systems to the first processor via the first host adaptor and the bridge, wherein the first processor maps the data routed thereto to an addressable area in the first group of DASDs;

directing data from at least one of the host systems to the second processor via the second host adaptor and bridge, wherein the second processor maps the data routed thereto to an addressable area in the second group of DASDs, wherein after configuration in response to determining that the second processor has failed, an I/O request from at least one of the host systems to the second group of DASDs is routed via the second host adaptor to the first processor, wherein the first processor maps the data routed to the second group of DASDs to the addressable area in the second group of DASDs.