Data bus having switch for selectively connecting and disconnecting devices to or from the bus

• US 6,061,754 A
• Filed: 06/25/1997
• Issued: 05/09/2000
• Est. Priority Date: 06/25/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Ekrot, Alexander C., Cepulis, Darren J., Tavallaei, Siamak
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Etienne, Ario
• Application Number:
  US08/882,615
• Time in Patent Office: 1,049 Days
• Field of Search: 395/306, 395/307, 395/311, 395/830, 395/831, 395/833, 395/853, 710/126, 710/127, 710/131, 710/10, 710/11, 710/13, 710/33, 710/129
• US Class Current: 710/312
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A data bus structure is disclosed. The structure includes a data bus having a bus agent connection point and a bus switch to selectively connect or disconnect the connection point to or from the data bus. A method of reconfiguring a data bus structure is also disclosed. The method includes providing two bus agent connection points on a data bus and a bus switch between the bus agent connection points and selecting the number of bus agent connection points on the bus by controlling the state of the bus switch.

Claims

1. A computer system comprising:

a first bus;

a second bus;

a first bridge coupled between the first bus and one end of the second bus;

a second bridge coupled between the first bus and an opposite end of the second bus; and

at least two switches coupled in the path of the second bus such that the second bus includes at least three portions, a first portion disposed between a first one of the switches and the first bridge, a second portion disposed between the first one of the switches and a second one of the switches, and a third portion disposed between the second one of the switches and the second bridge, wherein the second portion of the second bus is functionally coupled to either the first bridge or the second bridge based on the state of the at least two switches.

2. The system of claim 1 wherein said at least two switches includes bus signal termination functionality.

3. The system of claim 2 wherein said bus signal termination functionality comprises a resistive element selectively coupled to the second bus.

4. The system of claim 1 wherein the second bus has signal paths formed on a motherboard.

5. The system of claim 1 wherein the at least two switches comprise electronic bus switch components.

6. The system of claim 1 wherein the at least two switches comprise a circuit board that includes connectors to provide jumpers.

7. The system of claim 1 wherein the at least two switches comprise electro-mechanical relays.

8. The system of claim 1 wherein the at least two switches comprise cross-bar switches.

9. The system of claim 1 wherein the first bus comprises a processor host bus.

10. The system of claim 1 wherein the second bus comprises a PCI bus.

11. The system of claim 1 wherein the second bus comprises a SCSI bus.

12. The system of claim 1 wherein the first bridge communicates with the first portion of the second bus at one speed and wherein the second bridge communicates with the third portion of the second bus at a second speed.

13. The system of claim 12 wherein the first speed is about 33 MHz and the second speed is about 66 MHz.

14. The system of claim 1 wherein the at least two switches comprise more than two switches.

15. The system of claim 1 and further comprising a plurality of peripheral devices coupled to the second bus.

16. The system of claim 1 and further comprising monitoring circuitry to examine traffic between the first bus and the second bus and to cause the at least two switches to change states based upon the traffic.

17. A computer system comprising:

a first bus disposed on a circuit board;

a second bus disposed on the circuit board;

a third bus disposed on the circuit board;

a first bridge disposed on the circuit board and coupled between the first bus and the second bus;

a second bridge disposed on the circuit board and coupled between the first bus and the third bus; and

a plurality of bus agents, each bus agent coupled to a switch disposed on the circuit board the switch being configured to couple the bus agent to either the second bus or the third bus.

18. The system of claim 17 wherein the second bus and the third bus comprise PCI buses.

19. The system of claim 17 wherein the first bus comprises a host processor bus.

20. The system of claim 19 and further comprising at least one microprocessor coupled to the host processor bus.

21. The system of claim 17 wherein the switch is configurable in a third state such that a bus agent coupled to the switch is not coupled to either the second bus or the third bus.

22. A computer system that includes a bus structure with a reconfigurable length the system comprising:

a microprocessor coupled to a host bus;

an expansion bus disposed on a motherboard and including a plurality of bus agent connection points;

a bridge disposed on the motherboard and coupled to the expansion bus, each of the bus agent connection points accessible by the microprocessor through the bridge; and

a bus switch disposed on the motherboard and coupled in the expansion bus between at least one of the bus agent connection points and the bridge, wherein the computer system can operate in a first mode wherein the bus switch is closed and the at least one bus agent connection point is accessible to the microprocessor through the bridge or the computer can alternatively operate in a second mode wherein the bus switch is opened and the least one bus agent connection is not accessible to the microprocessor through the bridge.

23. The system of claim 22 wherein the bus switch includes bus signal termination functionality.

24. The system of claim 22 wherein the bus signal termination functionality comprises a resistive element selectively coupled to the bus.

25. The system of claim 22 wherein the bridge is connected to the host bus and is also connected to the expansion bus.

26. The system of claim 22 wherein the expansion bus is operating in a first bus operating frequency range when the switch is closed and operable in a second bus operating frequency range when the switch is closed, wherein the second bus operating frequency range has a greater maximum operating frequency that the first bus operating frequency range.

27. The system of claim 22 and further comprising a bus agent coupled to one of the bus agent connection points.

28. The system of claim 22 and further comprising a second bus switch coupled in the expansion bus.

29. A computer system comprising:

at least one microprocessor coupled to a host processor bus;

system memory coupled to the at least one microprocessor through the host processor bus;

an expansion bus;

a plurality of peripheral devices coupled to the expansion bus;

a first bridge coupled to one end of the expansion bus, at least one of the peripheral devices accessible by the at least one microprocessor through the first bridge;

a second bridge coupled to an opposite end of the expansion bus, at least another one of the peripheral devices accessible by the at least one microprocessor through the second bridge; and

at least two switches coupled in the path of the expansion bus such that the expansion bus includes at least three portions, a first portion disposed between a first one of the switches and the first bridge, a second portion disposed between the first one of the switches and a second one of the switches, and a third portion disposed between the second one of the switches and the second bridge, wherein the second portion of the expansion bus is functionally coupled to either the first bridge or the second bridge based on the state of the at least two switches.

30. The system of claim 29 wherein the expansion bus comprises a PCI bus.