Digital signal processor having data alignment buffer for performing unaligned data accesses

• US 6,061,779 A
• Filed: 01/16/1998
• Issued: 05/09/2000
• Est. Priority Date: 01/16/1998
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Garde, Douglas
• Primary Examiner(s): Treat, William M.
• Application Number:
  US09/008,154
• Time in Patent Office: 844 Days
• Field of Search: 712/200, 712/204
• US Class Current: 712/204
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing

Abstract

A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory may include first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and may include first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. A data alignment buffer is provided between the memory banks and the computation blocks. The data alignment buffer permits unaligned accesses to specified operands that are stored in different memory rows. The specified operands are supplied to one or both of the computation blocks in the same processor cycle.

Claims

1. A digital signal processor comprising:

a memory for storing data words including instructions and operands for performing digital signal computations, said memory organized in rows each having locations for two or more of said data words;

a program sequencer for generating instruction addresses for fetching instructions from said memory and data addresses for fetching operands from said memory;

a computation unit for performing said digital signal computations using said instructions and said operands fetched from said memory;

an instruction decoder for generating one or more control signals in response to an instruction indicating an unaligned data access to specified operands stored in different rows of said memory; and

a data alignment buffer for receiving lines of operands from different rows of said memory and for providing said specified operands to said computation unit in response to said one or more control signals, said one or more control signals including an offset value that identifies memory locations of the specified operands relative to a row of said memory, wherein different specified operands are selected from the different rows of said memory based on the offset value.

2. A digital signal processor as defined in claim 1, wherein said data alignment buffer comprises:

a buffer for storing a first line of operands from a first row of said memory; and

a multiplexer for receiving said first line of operands from said buffer and a second line of operands from a second row of said memory and for selecting said specified operands from said first and second lines of operands in response to said offset value.

3. A digital signal processor as defined in claim 2, wherein said computation unit includes a register file and wherein said multiplexer provides said specified operands to the register file.

4. A digital signal processor as defined in claim 1 wherein each row of said memory comprises four 32-bit data words.

5. A digital signal processor as defined in claim 1 wherein each row of said memory comprises eight 16-bit data words.

6. A digital signal processor as defined in claim 1, wherein said data alignment buffer further comprises means responsive to a sequence of instructions, each indicating an unaligned data access to specified operands, for providing said specified operands to said computation unit on successive processor cycles.

7. A digital signal processor as defined in claim 2 where said control signals further include a load signal supplied to said buffer.

8. A digital signal processor comprising:

a memory for storing data words including instructions and operands, said memory organized in rows each having locations for two or more of said data words;

a computation unit for performing digital signal computations using said instructions and said operands fetched from said memory; and

a data alignment buffer disposed between said memory and said computation unit for providing to said computation unit specified operands that are stored in different rows of said memory in response to an instruction indicating an unaligned data access, said instruction containing an offset value that identifies memory locations of the specified operands relative to a row of said memory, wherein different specified operands are selected from the different rows of said memory based on the offset value.

9. A digital signal processor as defined in claim 8, wherein said data alignment buffer comprises:

a buffer for storing a first line of operands from a first row of said memory; and

a multiplexer for receiving said first line of operands from said buffer and a second line of operands from a second row of said memory and for selecting said specified operands from said first and second lines of operands in response to said offset value.

10. A digital signal processor as defined in claim 9, wherein said computation unit includes a register file and wherein said multiplexer provides said specified operands to the register file.

11. A digital signal processor as defined in claim 8, wherein said data alignment buffer further comprises means responsive to a sequence of instructions, each indicating an unaligned data access to specified operands, for providing said specified operands to said computation unit on successive processor cycles.