Computer system with error handling before reset

• US 6,061,810 A
• Filed: 12/05/1996
• Issued: 05/09/2000
• Est. Priority Date: 09/09/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Potter, Mark R.
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US08/760,500
• Time in Patent Office: 1,251 Days
• Field of Search: 395/182.21, 395/185.08, 395/183.15, 395/183.08, 371/62, 714/23, 714/48
• US Class Current: 714/23
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection

Abstract

A computer system includes error handling hardware and software that logs the source of application program or system software errors before a reset occurs. Upon a catastrophic error, a retriggerable timer, which is periodically retriggered during normal system operation, instead times out causing a hardware reset. A predetermined time before this retriggerable timer times out, however, the microprocessor in the computer system is interrupted, and executes an interrupt routine in which it determines that the retriggerable timer is about to timeout, and logs the currently executing applications program or currently executing point in system software, as well as the actual location within the applications program or the system software. The reset subsequently occurs, but not before this information valuable for debugging and diagnosis is logged.

Claims

1. A method for logging errors before a hardware reset in a microcomputer system including a microprocessor with a hardware reset input and an interrupt input, the method comprising the steps of:

determining that a hardware reset will be provided to the hardware reset input;

providing an interrupt to the interrupt input a predetermined period of time before the hardware reset will be provided to the hardware reset input in response to determining that a hardware reset will be provided to the hardware reset input; and

executing an interrupt routine in response to said interrupt to log an error indicating operation of the interrupt routine.

2. The method of claim 1, wherein the microcomputer system further includes a reloadable timer with an indicator of time remaining until timeout, and wherein said step of determining that a hardware reset will be provided to the hardware reset input further comprises the steps of:

periodically reloading the reloadable timer during normal operation of the microcomputer system; and

if the indicator of time remaining until timeout falls below a predetermined threshold, indicating that it is determined that a hardware reset will be provided to the hardware reset input within the predetermined period of time.

3. The method of claim 1, wherein the microcomputer system further includes a reloadable timer and a delay timer with an output coupled to the microcomputer hardware reset input, and wherein said step of determining that a hardware reset will be provided to the hardware reset input further comprises the steps of:

periodically reloading the reloadable timer during normal operation of the microcomputer system; and

if the reloadable timer times out, indicating that it is determined that a hardware reset will be provided to the hardware reset input within the predetermined period of time and starting the delay timer.

4. The method of claim 1, wherein said step of executing an interrupt routine further comprises the steps of:

determining the address where the microprocessor was executing when said interrupt was provided to the microprocessor; and

logging a message indicative of where it was determined that the microprocessor was executing.

5. The method of claim 4, wherein the microcomputer system is running an operating system that maintains a list of loaded modules and wherein said step of determining the address further comprises the step of:

determining if and which of currently loaded modules was executing; and

wherein said step of logging further comprises the step of;

logging the determined loaded module'"'"'s name and execution address.

6. The method of claim 5, wherein the operating system is Netware and wherein said step of determining the address further comprises the step of:

determining if and which of currently loaded Netware Loadable Modules was executing; and

wherein said step of logging further comprises the step of;

logging the Netware Loadable Module name and execution address.

7. The method of claim 4, wherein said step of logging further comprises the step of:

writing said message to a non-volatile random access memory.

8. The method of claim 1, wherein said step of providing an interrupt further comprises the step of:

providing a non-maskable interrupt to the microprocessor.

9. A computer system that logs errors before a hardware reset, comprising:

a bus with data, address, and control lines;

a microprocessor with a reset input and an interrupt input, said microprocessor coupled to said bus;

a mass storage subsystem coupled to said bus for providing data to and storing data from said microprocessor over said bus;

a software module for periodic execution by said microprocessor, said software module, when periodically executed, periodically performs a predetermined operation;

a timer circuit providing a reset signal to the reset input in response to said software module failing to periodically perform the predetermined operation;

an interrupt circuit for providing an interrupt signal to the interrupt input a predetermined period of time before said timer circuit provides the reset signal; and

an error logging software module for execution by said microprocessor in response to the interrupt signal, said error logging software module, when executed, logging an error message.

10. The computer system of claim 9, wherein said error logging software module further comprises:

address determining code that, when executed, determines an address at which said microprocessor was executing when the interrupt signal was provided; and

logging code that, when executed, logs a message indicating the address.

11. The computer system of claim 10, wherein the computer includes a semi-permanent memory, wherein said error logging software module further comprises:

code for writing the error message to the semi-permanent memory.

12. The computer system of claim 9, wherein the computer includes a semi-permanent memory, wherein said error logging software module further comprises:

code for writing the error message to the semi-permanent memory.

13. The computer system of claim 9, wherein the computer system runs the Netware Operating System, and wherein said error logging software module is a Netware Loadable Module.

14. The computer system of claim 9, wherein the computer system runs an operating system that includes a list of loaded modules, and wherein said error logging software module further comprises:

module determining code for determining if and which of currently loaded modules was executing when the interrupt was provided; and

code for writing an error message containing the name of the determined executing loaded module.

15. The computer system of claim 9, wherein the computer system runs the Netware Operating System, and wherein said error logging software module further comprises:

Netware module determining code for determining if and which of currently loaded Netware Loadable Modules was executing when said interrupt signal was provided; and

code for writing an error message containing the name of the determined executing loaded module.

16. The computer system of claim 9 further comprising:

a network interface card coupled to said bus for communication with a network; and

a memory subsystem coupled to said bus for providing memory storage for said microprocessor.

17. The computer system of claim 9, wherein said timer circuit includes:

a reloadable timer with an indicator of time remaining until timeout,

wherein said interrupt circuit is responsive to the indicator indicating the predetermined period of time.

18. The computer system of claim 17, wherein the predetermined operation reloads the reloadable timer.

19. The computer system of claim 9, wherein said timer circuit includes:

a reloadable timer; and

a delay timer responsive to a timeout of the reloadable timer and for providing the reset signal to the reset input the predetermined period of time after the timeout of the reloadable timer,

wherein said interrupt circuit is responsive to the timeout of the reloadable timer.

21. The computer system of claim 9, wherein the interrupt signal is a non-maskable interrupt signal.

20. The computer system of 19, wherein the predetermined operation reloads the reloadable timer.