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Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers

  • US 6,061,814 A
  • Filed: 04/21/1998
  • Issued: 05/09/2000
  • Est. Priority Date: 04/21/1998
  • Status: Expired due to Term
First Claim
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1. A test structure for associating defects in a semiconductor process with individual metal layers, the semiconductor process having at least a first metal layer and a second metal layer for forming signal lines, the test structure comprising:

  • a first plurality of test logic gates coupled in a testable configuration by signal lines formed primarily of the first metal layer; and

    a second plurality of test logic gates coupled in a testable configuration by signal lines formed primarily of the second metal layer,the first plurality of test logic gates and the second plurality of test logic gates disposed on a single integrated circuit die.

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