Altering bit sequences to contain predetermined patterns

• US 6,061,818 A
• Filed: 05/08/1998
• Issued: 05/09/2000
• Est. Priority Date: 05/08/1997
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Touba, Nur A., McCluskey, Edward J.
• Primary Examiner(s): Tu, Trinh L.
• Assistant Examiner(s): LIN, SAMUEL K
• Application Number:
  US09/074,848
• Time in Patent Office: 732 Days
• Field of Search: 371/27.2, 371/22.4-22.6, 371/27.1, 371/27.4-27.5, 371/22.33, 371/22.32, 364/717
• US Class Current: 714/739
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR'"'"'s serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR'"'"'s for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.

Claims

1. A method implemented in an electronic circuit, the method comprising:

(a) generating a pseudorandom binary sequence of bit subsequences;

(b) producing from the bit subsequences a set of ternary sequences, wherein the ternary sequences comprise bit elements deterministically produced from the bit subsequences;

(c) deterministically altering the bit subsequences in accordance with the ternary sequences to produce altered bit sequences containing predetermined bit patterns; and

(d) applying the altered bit sequences to a circuit under test, wherein the ternary sequences are selected such that the altered bit sequences detect faults in the circuit under test.

2. The method of claim 1 wherein the bit elements include 1 elements, 0 elements, and X ("don'"'"'t care") elements.

3. The method of claim 1 wherein the ternary sequences depend further upon a predetermined circuit under test.

4. The method of claim 1 further comprising shifting the altered bit sequences into a scan path associated with a circuit under test.

5. The method of claim 1 wherein the ternary sequences are produced by decoding the bit subsequences using a combinational logic circuit.

6. The method of claim 1 wherein the altering of the bit subsequences comprises performing logical operations between bits in the subsequences and the bit elements in the ternary sequences.

7. The method of claim 1 further comprising repeating step (a) to generate different pseudorandom sequences.

8. The method of claim 1 wherein the generating of the bit subsequences is performed by one or more linear feedback shift registers.

9. The method of claim 1 wherein the generating of the bit subsequences is performed by a cellular automaton.

10. An electronic circuit comprising:

(a) means for generating a pseudorandom binary sequence of bit subsequences;

(b) means for producing ternary sequences in response to the means for generating the binary sequence, wherein the ternary sequences comprise bit elements deterministically produced from the bit subsequences;

(c) means for deterministically altering the bit subsequences in accordance with the ternary sequences, resulting in an altered bit sequence containing predetermined bit patterns; and

(d) means for applying the altered bit subsequences to a circuit under test, wherein the ternary sequences are produced to detect faults in the circuit under test by the applied altered sequence.

11. The circuit of claim 10 wherein the ternary sequences of bit elements include 1 elements, 0 elements, and X ("don'"'"'t care") elements.

12. The circuit of claim 10 wherein the ternary sequences are selected to detect faults in a circuit under test.

13. The circuit of claim 10 wherein the means for producing ternary sequences of bit elements comprises a combinational logic circuit connected to the means for generating the binary sequence.

14. The circuit of claim 10 wherein the means for producing predetermined ternary sequences comprises:

a ternary sequence selection logic circuit;

a ternary sequence identification register circuit; and

a ternary sequence generation logic circuit.

15. The circuit of claim 10 wherein the means for altering the bit subsequences comprises a logic gate adapted to perform logical operations between bits in the subsequences and bit elements in the ternary sequences.

16. The circuit of claim 10 wherein the means for generating the bit sequence comprises a ROM.

17. The circuit of claim 10 wherein the means for generating the bit sequence comprises one or more linear feedback shift registers.

18. The circuit of claim 10 wherein the means for generating the bit sequence comprises a cellular automaton.

19. The circuit of claim 10 further comprising a set of scan paths fed by different stages of the means for generating the bit sequence.