Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits

• US 6,063,698 A
• Filed: 06/30/1997
• Issued: 05/16/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Tobin, Philip J., Tseng, Hsing-Huang
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US08/885,433
• Time in Patent Office: 1,051 Days
• Field of Search: 438/585, 438/591, 438/594, 438/595, 438/709, 438/711, 438/712, 438/669, 438/660, 438/706, 438/710, 438/708, 438/715, 438/719, 438/910
• US Class Current: 438/585
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 438/91 Controlling charging state at semiconductor-insulator interface

Abstract

A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750° C. and 850° C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.

Claims

1. A method for forming a semiconductor structure, the method comprising the steps of:

providing a substrate having a surface;

forming a high-k dielectric layer over the substrate, the high-k dielectric layer having bulk traps and interface traps;

forming a gate layer over the high-k dielectric layer;

etching the gate layer in a plasma environment to form a gate region, wherein the step of etching causes a plasma etch damage in the substrate; and

performing a low temperature wet oxidation step to inactivate the bulk traps and interface traps associated with the high-k dielectric layer, and to reduce the plasma etch damage.

2. The method of claim 1, wherein the step of forming the high-k dielectric layer comprises:

using a chemical vapor deposition (CVD) process to form the high-k dielectric layer.

3. The method of claim 2, wherein the step of forming a high-k dielectric layer comprises:

forming the high-k dielectric layer with a relative permitivity of greater than approximately 5.

4. The method of claim 2, wherein the step of forming the high-k dielectric layer comprises:

using a jet vapor deposition process as the CVD process to form the high-k dielectric layer.

5. The method of claim 1, wherein the step of forming the high-k dielectric layer comprises:

using a sputtering process to form the high-k dielectric layer.

6. The method of claim 1, wherein the step of forming the high-k dielectric layer comprises:

forming the high-k dielectric layer having an SiO2 equivalent thickness of less than approximately 40 angstroms.

7. The method of claim 1, wherein the step of forming the high-k dielectric layer comprises:

forming the high-k dielectric layer to include an oxide.

8. The method of claim 7, wherein the step of forming the high-k dielectric layer comprises:

forming the high-k dielectric layer to further include silicon nitride.

9. The method of claim 7, wherein the step of forming the high-k dielectric layer comprises:

forming the high-k dielectric layer wherein the oxide is a metal oxide.

10. The method of claim 9, wherein the step of forming the high-k dielectric layer comprises:

forming a Titanium oxide as the metal oxide.

11. The method of claim 9, wherein the step of forming the high-k dielectric layer comprises:

forming a Tantalum oxide as the metal oxide.

12. The method of claim 1, wherein the step of performing the low temperature wet oxidation comprises:

performing the low temperature wet oxidation step at a temperature in a range of approximately 750°

to 850°

Celsius.

13. The method of claim 1, wherein the step of performing the low temperature wet oxidation comprises:

introducing approximately 3 to 9 molecular percentage of hydrogen to oxygen.

14. The method of claim 1, wherein the step of etching the gate layer further includes etching the gate layer using a reactive ion etch (RIE).

15. The method of claim 1, wherein the step of forming a high-k dielectric layer comprising:

forming the high-k dielectric layer to have a relative permitivity of greater than approximately 8.

16. The method of claim 1, further comprising a step of:

performing an anneal that includes Nitrogen.

17. The method of claim 16, wherein the step of perfoming the anneal comprises:

performing the anneal in situ with the low temperature wet oxidation step.

18. A method for forming a semiconductor structure, the method comprising the steps of:

providing a substrate having a surface;

forming a dielectric layer over the substrate using a chemical vapor deposition (CVD), wherein a the CVD process causes a formation of bulk traps and interface traps;

forming a gate layer over the dielectric layer;

etching the gate layer and the dielectric layer in a plasma environment to form a gate region, wherein the plasma environment at least partially causes a first leakage current between the gate and the substrate; and

performing a low temperature wet oxidation to reduce the bulk traps and interface traps, wherein there is a second leakage current between the gate and substrate following the step of performing a low temperature wet oxidation and the second leakage current is less than the first leakage current.

19. A method for forming a semiconductor structure, the method comprising the steps of:

forming a dielectric layer having an oxide equivalent thickness of less than approximately 40 Angstroms over a semiconductor substrate;

forming a gate layer;

etching the gate layer and the dielectric layer, by a plasma etch process, to form a patterned gate structure;

placing the semiconductor substrate in an oxidation chamber;

heating the oxidation chamber to approximately 750°

to 850°

Celsius;

introducing oxygen into the oxidation chamber;

introducing a diluted amount of hydrogen into the oxidation chamber at a substantially same time as the oxygen; and

maintaining 750°

to 850°

Celsius in the oxidation chamber for approximately 15 minutes.

20. The method of claim 19,

the oxygen is introduced at a rate of 20 standard liters per minute (SLM);

and

the diluted amount of hydrogen is introduce at a rate of 10 SLM.