RF power MOSFET device with extended linear region of transconductance characteristic at low drain current

• US 6,064,088 A
• Filed: 06/15/1998
• Issued: 05/16/2000
• Est. Priority Date: 06/15/1998
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Xemod, Inc. (Qorvo, Inc.)
• Inventors: D'Anna, Pablo Eugenio
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/097,532
• Time in Patent Office: 701 Days
• Field of Search: 257/343, 257/355, 257/341, 257/383
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor MOSFET device having a decreased length of the channel region is disclosed. In one embodiment of the device, each gate includes three gate subregions. An enhancement drift drain region underlies the first gate subregion, a channel region underlies the third gate subregion, and each enhancement drift drain region and each channel region are separated by an epitaxial region underlying the second gate subregion. The device of the present invention if used as an amplifier, has a more linear transfer characteristic, less cross talk and less channel interference than a conventional semiconductor MOSFET device having a conventional gate region without gate subregions.

Claims

1. A lateral RF MOS transistor having a plug connective structure comprising:

a semiconductor material of a first conductivity type, said semiconductor material having a first dopant concentration and a top surface;

a conductive gate overlying and insulated from said top surface of said semiconductor material, said gate further comprising;

a first gate region;

a second gate region; and

a third gate region;

a first region formed completely within said semiconductor material of said first conductivity type, said first region being of a second conductivity type and having a second dopant concentration to form an enhanced drain drift region of said RF MOS transistor structure, said enhanced drain drift region underlying said first gate region;

a second region formed in said semiconductor material, said second region being of said second conductivity type and having a third dopant concentration greater than said second dopant concentration to form a drain region of said RF MOS transistor, said second region contacting said first region;

a third region formed in said semiconductor material, said third region being of said first conductivity type and having a fourth dopant concentration to form a body region of said RF MOS transistor structure, said fourth dopant concentration being equal or greater than said first dopant concentration, said body region further including;

a channel region formed in said body region when a voltage is applied to said gate, said channel region underlying said third gate region;

a fourth region formed in said semiconductor material, said fourth region being of said second conductivity type and having a fifth dopant concentration to form a source region of said RF MOS transistor structure, said fourth region being located within said third region;

a fifth region formed in said semiconductor material, said fifth region being of said first conductivity type and having a sixth dopant concentration to form a contact enhancement region of said RF MOS transistor structure, said sixth dopant concentration being greater than said fourth dopant concentration of said third region, said fifth region being located within said third region; and

a conductive plug region formed in said source region and said body region of said semiconductor material;

wherein a remaining portion of said epitaxial layer underlying said second gate region is of said first conductivity type; and

wherein said enhanced drain drift region and said channel region are separated by said remaining portion of said epitaxial layer.

3. The semiconductor device of claim 1, wherein said first conductivity type is a P type.

4. The semiconductor device of claim 1, wherein said first conductivity type is an N type.

5. The semiconductor device of claim 1, wherein:

each said drain region is more heavily doped than each said enhanced drift drain region.

6. The semiconductor device of claim 1, wherein:

each said body region is more heavily doped than said epitaxial layer.

7. The semiconductor device of claim 1, wherein:

each said drain region and each said source region are equally doped.

2. A lateral RF MOS transistor having a quasi-mesh gate structure comprising:

a semiconductor material of a first conductivity type, said semiconductor material having a first dopant concentration and a top surface;

a plurality of conductive gates, each said gate overlying and being insulated from said top surface of said semiconductor material, each said gate further comprising;

a first gate region;

a second gate region; and

a third gate region;

a plurality of first regions formed completely within said semiconductor material of said first conductivity type, said first regions being of a second conductivity type and a second dopant concentration to form substantially identical enhanced drain drift regions of said lateral RF MOS transistor, each said first region underlying one said first gate region;

a plurality of second regions formed in said semiconductor material, said second regions being of said second conductivity type and a third dopant concentration greater than said second dopant concentration to form substantially identical drain regions of said lateral RF MOS transistor, wherein each of said second regions contacts a respective one of said first regions,

a plurality of third regions formed in said semiconductor material, said third regions being of said first conductivity type and a fourth dopant concentration to form substantially identical body regions of said lateral RF MOS transistor, said fourth dopant concentration being equal or greater than said first dopant concentration, each said body region further including;

a channel region formed in said body region when a voltage is applied to said RF MOS device, said channel region underlying one said third gate region;

wherein a remaining portion of said epitaxial layer underlying each said second gate region is of said first conductivity type; and

wherein each said enhanced drain drift region and each said channel region are separated by said remaining portion of said epitaxial layer;

a plurality of fourth regions formed in said semiconductor material, each of said fourth regions being of said second conductivity type and a fifth dopant concentration to form substantially identical source regions of said lateral RF MOS transistor, each of said fourth regions located within a respective one of said third regions;

a plurality of fifth regions formed in said semiconductor material, each of said fifth regions being of said first conductivity type and a sixth dopant concentration to form substantially identical body contact enhancement regions of said lateral RF MOS transistor, said sixth dopant concentration being greater than said fourth dopant concentration, each of said fifth regions being located within a respective one of said third regions;

a plurality of conductive plug regions, each said conductive plug region being formed in a respective one of said source regions and said body regions, each said conductive plug region being used to connect one said source region and one said body region of said semiconductor material to a backside of said lateral RF MOS transistor;

a layer of an insulator covering said top surface of said semiconductor material, said insulator layer including a first plurality of openings and a second plurality of openings;

said first plurality of openings used to expose each said gate region;

said second plurality of openings used to expose each said drain region;

a first plurality of metal fingers used to connect each said exposed drain region to a first side of said RF MOS transistor; and

a second plurality of metal fingers used to connect each said exposed gate region to a second side of said RF MOS transistor.