Thin film transistors having an active region composed of intrinsic and amorphous semiconducting layers

• US 6,064,091 A
• Filed: 12/10/1998
• Issued: 05/16/2000
• Est. Priority Date: 12/10/1997
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Shannon, John M., Deane, Steven C.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/209,085
• Time in Patent Office: 523 Days
• Field of Search: 257/331-344, 257/347-351, 257/52, 257/55, 257/57, 257/66
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor (10) in an electronic device such as an active matrix display panel having an intrinsic amorphous silicon semiconductor layer (22) providing a channel region (23) between source and drain electrodes (14, 16) includes directly adjacent to the side of the semiconductor layer (22) remote from the gate electrode (25) at the channel region (23) a layer (20) of amorphous semiconductor material which has a high defect density and low conductivity that serves to provide recombination centres for photogenerated carriers. Leakage problems due to the photoconductive properties of the intrinsic semiconductor material are then reduced. Conveniently, an hydrogenated silicon rich amorphous silicon alloy (e.g. nitride etc) can be used for the recombination centre layer (20).

Claims

1. An electronic device comprising a thin film transistor carried on a transparent, insulating, substrate, and having spaced source and drain electrodes, an intrinsic amorphous silicon semiconductor layer extending between the source and drain electrodes for providing a channel region between the source and drain electrodes, and a gate insulator layer and gate electrode extending adjacent to the intrinsic semiconductor layer, characterised in that the channel region of the intrinsic semiconductor layer at its side remote from the gate electrode extends directly adjacent to a layer of amorphous semiconductor material having a high defect density and low conductivity and which serves to provide recombination centres for photogenerated carriers.

2. An electronic device according to claim 1, characterised in that said layer of amorphous semiconductor material having a high defect density comprises a silicon rich amorphous silicon alloy material.

3. An electronic device according to claim 2, characterised in that said silicon rich material comprises silicon nitride material.

4. An electronic device according to claim 2, characterised in that said silicon rich material comprises silicon carbide material.

5. An electronic device according to claim 2, characterised in that said silicon rich material comprises silicon oxide material.

6. An electronic device according to claim 2, characterised in that said silicon rich material comprises silicon oxynitride material.

7. An electronic device according to claim 2, characterised in that said silicon rich material comprises amorphous silicon germanium.

8. An electronic device according to claim 1, characterised in that the TFT comprises a top gate TFT in which the gate electrode is provided at the side of the intrinsic semiconductor layer remote from the substrate.

9. An electronic device according to claim 8, characterised in that the source and drain electrodes are situated at the opposite side of the intrinsic semiconductor layer from the gate electrode.

10. An electronic device according to claim 1, characterised in that device comprises a plurality of said TFTs carried on said substrate.

11. An electronic device according to claim 10, characterised in that the electronic device comprises an active matrix liquid crystal display device having an array of picture elements addressed by sets of address conductors carried on the substrate, each picture element comprising a said TFT whose source and gate electrodes are connected to respective address conductors and whose drain is connected to a picture element electrode.