Semiconductor device having a sub-chip-scale package structure and method for forming same

• US 6,064,114 A
• Filed: 12/01/1997
• Issued: 05/16/2000
• Est. Priority Date: 12/01/1997
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Higgins, III, Leo M.
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US08/980,783
• Time in Patent Office: 897 Days
• Field of Search: 257/782, 257/783, 257/778, 257/777, 257/685, 257/686, 257/786, 257/785
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/07811 Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor device (1) has a sub-chip-scale package structure, wherein the substrate (50) has at least one of an X dimension and a Y dimension smaller than a corresponding dimension of the semiconductor die (10). The semiconductor device (1) has a plurality of electrical connections between the semiconductor die and the substrate, the electrical connections (15, 20) being provided within the outer periphery of the substrate. The semiconductor device (1) permits packaging of semiconductor die (10) at the wafer level, that is, before the semiconductor die are singulated.

Claims

1. A semiconductor device, comprising:

a semiconductor die having a surface, and outer periphery X and outer periphery Y dimensions, the outer periphery X and outer periphery Y dimensions of the semiconductor die being perpendicular to each other;

a plurality of electrical contacts on the surface of the semiconductor die; and

a package substrate overlying the semiconductor die and being electrically connected to the plurality of electrical contacts, wherein;

the package substrate has outer periphery X'"'"' and outer periphery Y'"'"' dimensions being perpendicular to each other, at least one of (i) the outer periphery X'"'"' dimension of the package substrate is less than the outer periphery X dimension of the semiconductor die, and (ii) the outer periphery Y'"'"' dimension of the package substrate is less than the outer periphery Y dimension of the semiconductor die, and the plurality of electrical contacts are located within the outer periphery X dimension and the outer periphery Y dimension of the package substrate.

2. The semiconductor device of claim 1, wherein both (i) the outer periphery X'"'"' dimension of the package substrate is less than the outer periphery X dimension of the semiconductor die, and (ii) the outer periphery Y'"'"' dimension of the package substrate is less than the outer periphery Y dimension of the semiconductor die.

3. The semiconductor device of claim 1, further comprising an underfill encapsulation layer between the semiconductor die and the package substrate.

4. The semiconductor device of claim 3, wherein the package substrate has an outer peripheral surface, and the underfill encapsulation layer forms a fillet extending along the outer peripheral surface of the package substrate.

5. The semiconductor device of claim 1, wherein the plurality of electrical contacts comprises metal bumps.

6. The semiconductor device of claim 5, wherein the plurality of metal bumps comprises solder.

7. The semiconductor device of claim 1, wherein the package substrate includes an insulating layer having a first surface and a second surface opposite the first surface, a plurality of direct chip attach bond pads on the first surface, a plurality of ball grid array bond pads on the second surface, a plurality of electrical interconnections that interconnect the plurality of direct chip attach bond pads to the plurality of ball grid array bond pads, and a plurality of ball grid array balls respectively attached to the plurality of ball grid array bond pads.

8. The semiconductor device of claim 7, wherein the plurality of electrical interconnections extends through the package substrate.

9. The semiconductor device of claim 1, wherein the semiconductor die has an outer periphery, the semiconductor die further comprising a plurality of circuit contact pads arranged adjacent the outer periphery and a plurality of redistribution traces extending from the plurality of circuit contact pads toward a central portion of the semiconductor die.

10. The semiconductor device of claim 1, wherein the package substrate includes an insulating layer, the insulating layer comprising a material from a group consisting of organic polymer and ceramic.

11. The semiconductor device of claim 10, wherein said material is an organic polymer.

12. A semiconductor device, comprising:

a semiconductor die having a surface, and X and Y dimensions, the X and Y dimensions of the semiconductor die being perpendicular to each other;

a plurality of electrical contacts on the surface of the semiconductor die; and

a substrate having a plurality of electrical connections between conductive portions of a first outer surface and conductive portions of a second outer surface, the first outer surface is between and adjacent to the second outer surface and the surface of the semiconductor die, wherein one of the plurality of electrical connections of the substrate is electrically connected to at least one of the plurality of electrical contacts on the surface of the semiconductor die, wherein the first outer surface of the substrate has X'"'"' and Y'"'"' dimensions being perpendicular to each other, and at least one of (i) the X'"'"' dimension of the first outer surface substrate is less than the X dimension of the semiconductor die, and (ii) the Y'"'"' dimension of the first outer surface substrate is less than the Y dimension of the semiconductor die, furthermore, the substrate has an outer periphery, and the plurality of electrical contacts are located within the outer periphery of the substrate.

13. The semiconductor device of claim 12, wherein the plurality of electrical contacts comprises metal bumps.

14. The semiconductor device of claim 13, wherein the plurality of metal bumps comprises solder.

15. The semiconductor device of claim 12, further comprising an underfill encapsulation layer between the semiconductor die and the substrate.

16. The semiconductor device of claim 15, wherein both (i) the X'"'"' dimension of the substrate is less than the X dimension of the semiconductor die, and (ii) the Y'"'"' dimension of the substrate is less than the Y dimension of the semiconductor die.

17. The semiconductor device of claim 15, wherein the substrate has an outer peripheral surface, and the underfill encapsulation layer forms a fillet extending along the outer peripheral surface of the substrate.

18. A semiconductor device comprising:

first cross-sectional component along a first line perpendicular the surface of the device and a second cross-sectional component along a second line perpendicular the surface of the device,

from the first surface to the second surface, the first cross sectional component including the following layers

a first conductive pad;

an insulator;

an encapsulation material; and

a semiconductor die;

from the first surface to the second surface, the second cross sectional component including the following layers

the encapsulation material forming a part of the first surface;

the semiconductor die immediately adjacent to the encapsulation material.

19. The semiconductor device of claim 18, wherein the first conductive pad is a ball grid array pad.

20. The semiconductor device of claim 18, wherein the first cross sectional component includes a solder bump forming a part of the first surface, such that the first conductive pad is between the solder bump and the insulator.