Voltage regulator compensation circuit and method

• US 6,064,187 A
• Filed: 02/12/1999
• Issued: 05/16/2000
• Est. Priority Date: 02/12/1999
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Analog Devices, Inc.
• Inventors: Reizik, Gabor, Audy, Jonathan M., Erisman, Brian P., Redl, Richard
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US09/249,266
• Time in Patent Office: 459 Days
• Field of Search: 323/285, 323/224
• US Class Current: 323/285
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence

Abstract

A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator'"'"'s output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.

Claims

1. A method of enabling a voltage regulator to employ the smallest possible output capacitor that allows the regulator'"'"'s output voltage to be maintained within specified boundaries for bidirectional step changes in load current of a specified maximum magnitude, comprising the step of:

compensating a voltage regulator which employs an output capacitor and is required to maintain a regulated output voltage within specified boundaries for bidirectional step changes in load current of a specified maximum magnitude such that, after the occurrence of a step change in load current of said specified maximum magnitude, its output voltage response is flat after its output voltage reaches one of said specified boundaries, the output capacitor required to provide said compensation being the smallest possible output capacitor that allows the regulator'"'"'s output voltage to be maintained within said specified boundaries.

2. A method of minimizing the size of a voltage regulator'"'"'s output capacitor which enables the regulator'"'"'s output voltage to be maintained within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, comprising the steps of;

selecting a type of capacitor to be used as the output capacitor for a voltage regulator connected to provide a regulated output voltage to an output load at an output node, said output capacitor to be connected in parallel across said load, said regulator required to maintain a regulated output voltage within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load,

determining the characteristic time constant T_c for the selected capacitor type,

determining the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to Δ

I_load and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to Δ

I_load,

determining which of said absolute values is smaller, the smaller of said absolute values being a value m,

determining a first capacitance C₀ in accordance with the following;

C₀ =[Δ

I_load² /2m+mT_c² /2]/Δ

V_out

determining a resistance R_e0 in accordance with the following;

R_e0 =T_c /C₀

determining a critical capacitance C_crit in accordance with the following;

C_crit =Δ

I_load /mR_e0,

selecting an output capacitor for connection across said load having a capacitance C₁ about equal to C₀ and an equivalent series resistance R_e1 about equal to R_e0 if C₀ is less than C_crit,

selecting an output capacitor for connection across said load having a capacitance C₂ about equal to T_c /R_e0 and an equivalent series resistance R_e2 about equal to Δ

V_out /Δ

I_load if C₀ is equal to or greater than C_crit,

determining a resistance R_o in accordance with the following if C₀ is less than C_crit ;

space="preserve" listing-type="equation">R.sub.o =Δ

I.sub.load /2mC.sub.1 +[mC.sub.1 R.sub.e1 ]/2Δ

I.sub.load

determining a resistance R_o in accordance with the following if C₀ is equal to or greater than C_crit ;

R_o =R_e2, and

arranging the voltage regulator such that its output impedance, defined before its connection to the selected output capacitor, is about equal to the series combination of resistance R_o and an inductance L_o, with L_o given by the following if C₀ is less than C_crit ;

space="preserve" listing-type="equation">L.sub.o =C.sub.1 *R.sub.e1 *R.sub.o,

or given by the following if C₀ is equal to or greater than C_crit ;

L_o =C₂ *R_e2 *R_o.

3. The method of claim 2, wherein said voltage regulator is a buck-type switching voltage regulator having an output inductor with an inductance L and which receives an input voltage V_in and produces an output voltage V_out, said value of m given by m=V_out /L if V_out is less than V_in -V_out and by (V_in -V_out /L if V_out is greater than V_in -V_out.

4. The method of claim 2, wherein said voltage regulator includes a controllable power stage which provides the regulator'"'"'s output voltage in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage having a transconductance g, said step of arranging said output impedance to be about equal to the series combination of resistance R_o and inductance L_o accomplished by making the gain K(s) of said voltage error amplifier equal to the following:

space="preserve" listing-type="equation">K(s)=(-1/gR.sub.o)(1/(1+sR.sub.e C))

in which C and R_e are the capacitance and equivalent series resistance of the output capacitor employed.

5. The method of claim 2, wherein said voltage regulator includes an impedance Z1 connected between said output node and a first node, an impedance Z2 connected between said first node and a reference voltage, a current sensor which has a transresistance R_s and produces an output that varies with the output current delivered to said load, a summing circuit which produces an output voltage equal to the sum of the current sensor output voltage and the regulator'"'"'s output voltage, and a controllable power stage which provides the regulator'"'"'s output voltage in accordance with the voltage difference between the voltage at said first node and said summing circuit output voltage, said step of arranging said output impedance to be about equal to the series combination of resistance R_o and inductance L_o accomplished by making the ratio of impedances Z1 and Z2 equal to the following:

space="preserve" listing-type="equation">Z2/Z1=[R.sub.o (1+sR.sub.e C)-R.sub.s ]/R.sub.s

in which C and R_e are the capacitance and equivalent series resistance of the output capacitor employed.

6. A method of minimizing the size of a voltage regulator'"'"'s output capacitor which enables the regulator'"'"'s output voltage to be maintained within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, comprising the steps of;

calculating a maximum equivalent series resistance R_e(max) for an output capacitor to be employed by a voltage regulator which provides an output voltage to a load at an output node, said output capacitor to be connected in parallel across said load, said regulator required to maintain said output voltage within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, R_e(max) calculated in accordance with the following;

R_e(max) =Δ

V_out /Δ

I_load,

determining the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to Δ

I_load and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to Δ

I_load,

determining which of said absolute values is smaller, the smaller of said absolute values being a value m,

determining a critical capacitance C_crit in accordance with the following;

C_crit =Δ

I_load /mR_e(max),

selecting an output capacitor for connection across said load having an equivalent series resistance R_e that is slightly less than or equal to R_e(max) and a capacitance that is greater than or equal to C_crit, and

arranging the output impedance of said voltage regulator to be about equal to R_e.

7. The method of claim 6, wherein said voltage regulator includes a controllable power stage which provides the regulator'"'"'s output voltage in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage characterized by a transconductance g, said step of arranging said output impedance to be about equal to R_e accomplished by making the gain K(s) of said voltage error amplifier equal to the following:

space="preserve" listing-type="equation">K(s)=(-1/gR.sub.e)(1/(1+sR.sub.e C))

in which C and R_e are the capacitance and equivalent series resistance of the output capacitor employed.

8. A method of minimizing the size of a buck-type switching voltage regulator'"'"'s output capacitor which enables the regulator'"'"'s output voltage V_out to be maintained within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, comprising the steps of;

calculating a maximum equivalent series resistance R_e(max) for an output capacitor to be employed by a current-mode controlled switching voltage regulator which receives an input voltage V_in and provides an output voltage V_out to a load connected to an output node via an output inductor, said inductor alternately connected to V_in and ground via first and second switches, respectively, said output capacitor to be connected in parallel across said load, said regulator required to maintain V_out within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, R_e(max) calculated in accordance with the following;

R_e(max) =Δ

V_out /Δ

I_load,

determining a minimum inductance L_min for said output inductor in accordance with the following;

space="preserve" listing-type="equation">L.sub.min =V.sub.out T.sub.off R.sub.e(max) /V.sub.ripple,p-p

where T_off is the off time of said first switch and V_ripple,p-p is the maximum allowed peak-to-peak output ripple voltage,

selecting an output inductor for use in said regulator having an inductance L1 which is equal to or greater than L_min,

determining a minimum capacitance C_min for said output capacitor in accordance with the following;

space="preserve" listing-type="equation">C.sub.min =Δ

I.sub.load [R.sub.e(max) (V.sub.out /L1)] if V.sub.out <

(V.sub.in -V.sub.out)

and in accordance with the following;

space="preserve" listing-type="equation">C.sub.min =Δ

I.sub.load [R.sub.e(max) ((V.sub.in -V.sub.out)/L1)] if V.sub.out >

V.sub.in -V.sub.out,

selecting an output capacitor for connection across said load having a capacitance C about equal to C_min and an equivalent series resistance R_e about equal to R_e(max), and

arranging the output impedance of said regulator to be about equal to R_e.

9. The method of claim 8, wherein said voltage regulator includes a controllable power stage which provides the regulator'"'"'s output voltage in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage characterized by a transconductance g, said step of arranging said output impedance to be about equal to R_e accomplished by making the gain K(s) of said amplifier equal to the following:

space="preserve" listing-type="equation">K(s)=(-1/gR.sub.e)(1/(1+sR.sub.e C))

in which C and R_e are the capacitance and equivalent series resistance of the output capacitor employed.

10. A voltage regulator which maintains its output voltage within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, comprising;

a controllable power stage characterized by a transconductance g and connected to produce an output voltage V_out at an output node in accordance with a signal received at a control input, said output node connected to a load,

an output capacitor connected to said output node and in parallel across said load, said output capacitor having an equivalent series resistance R_e, and

a voltage error amplifier connected between said output node and said control input, said controllable power stage, said output capacitor and said amplifier forming a voltage regulator required to maintain the voltage at said output node within a specified voltage deviation specification Δ

V_out for a step change in load current Δ

I_load,

said output capacitor having a capacitance that is equal to or greater than a critical capacitance C_crit, in which C_crit is given by the following;

C_crit =Δ

I_load /mR_e, where m is equal to the smaller of

     1) the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to Δ

I_load, or

     2) the absolute value of the minimum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to Δ

I_load, said voltage regulator arranged to have an output impedance which is about equal to R_e.

11. The voltage regulator of claim 10, wherein the gain K(s) of said voltage error amplifier is given by the following:

space="preserve" listing-type="equation">K(s)=(-1/gR.sub.e)(1/(1+sR.sub.e C))

where g is equal to the transconductance of said controllable power stage, and R_e and C are equal to the equivalent series resistance and capacitance, respectively, of said output capacitor.

12. The voltage regulator of claim 10, wherein said controllable power stage comprises a power circuit connected to produce said regulator'"'"'s output voltage in accordance with a signal received at a control input, a current sensor connected in series between said power circuit and said output node which produces an output that varies with said power circuit'"'"'s output current, and a current controller connected to receive the outputs of said voltage error amplifier and said current sensor as inputs and producing an output connected to said power circuit'"'"'s control input for controlling said power circuit.

13. The voltage regulator of claim 12, wherein said current controller is an amplifier and said power circuit is a series pass transistor, said regulator being a linear voltage regulator.

14. The voltage regulator of claim 10, wherein said regulator is a switching voltage regulator.

15. The voltage regulator of claim 10, wherein said output capacitor has a capacitance about equal to C_crit and an equivalent series resistance R_e about equal to Δ

V_out /Δ

I_load, said capacitor being the smallest possible output capacitor which enables the regulator to maintain its output voltage within Δ

V_out for a step change in load current Δ

I_load.

16. A voltage regulator which maintains a regulated output voltage within a specified voltage deviation specification Δ

V_out for a bidirectional step change in load current Δ

I_load, comprising;

a controllable power stage characterized by a transconductance g and connected to produce an output voltage V_out at an output node in accordance with a signal received at a control input, said output node connected to an output load,

an output capacitor connected to said output node and in parallel across said output load, and

a voltage error amplifier connected between said output node and said control input, said power stage, said output capacitor and said amplifier forming a voltage regulator required to maintain a voltage at said output node within a specified voltage deviation specification Δ

V_out for a step change in load current Δ

I_load, said amplifier arranged to have a gain K(s) given by the following;

space="preserve" listing-type="equation">K(s)=(-1/gR.sub.o)(1/(1+sR.sub.e C))

where g is equal to the transconductance of said controllable power stage, R_e and C are equal to the equivalent series resistance and capacitance, respectively, of said output capacitor, and where R_o is equal to;

R_e, if C is greater than or equal to Δ

I_load /mR_e, or to;

space="preserve" listing-type="equation">Δ

I.sub.load /2mC+[mC(R.sub.e)]/2Δ

I.sub.load, if C is less than Δ

I.sub.load /mR.sub.e,

where m is equal to the smaller of

     1) the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to Δ

I_load, or

     2) the absolute value of the minimum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to Δ

I_load.

17. A voltage regulator which maintains a regulated output voltage within a specified voltage deviation specification Δ

V_out for a step change in load current Δ

I_load, said regulator comprising;

a controllable power stage which provides an output voltage to a load at an output node in accordance with the voltage difference between a first control input and a second control input,

an output capacitor connected to said output node and in parallel across said load,

an impedance Z1 connected between said output node and a first node,

an impedance Z2 connected between said first node and a reference voltage,

a current sensor which has a transresistance R_s and produces an output voltage that varies with the output current delivered to said load,

a summing circuit which produces an output voltage equal to the sum of the sensor output voltage and the voltage at said output node, said current sensor output voltage and said summing circuit output voltage connected to said first and second control inputs, respectively, said controllable power stage, said output capacitor, said impedances, said current sensor and said summing circuit forming a voltage regulator required to maintain the voltage at said output node within a specified voltage deviation specification Δ

V_out for a step change in load current Δ

I_load, said regulator arranged such that the ratio of impedances Z1 and Z2 is equal to the following;

space="preserve" listing-type="equation">Z1/Z2=[R.sub.o (1+sR.sub.e C)-R.sub.s ]/R.sub.s

where R_e and C are equal to the equivalent series resistance and capacitance, respectively, of said output capacitor, and where R_o is equal to;

R_e, if C is equal to or greater than Δ

I_load /mR_e, or to;

space="preserve" listing-type="equation">Δ

I.sub.load /2mC+[mC(R.sub.e)]/2Δ

I.sub.load, if C is less than Δ

I.sub.load /mR.sub.e,

where m is equal to the smaller of

     1) the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to Δ

I_load, or

     2) the absolute value of the minimum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to Δ

I_load.

18. The voltage regulator of claim 17, wherein said controllable power stage comprises:

a power circuit connected to produce said regulator'"'"'s output voltage in response to a signal received at a control input, and

a fast voltage controller producing an output signal to said control input of said power circuit in accordance with the voltage difference between the voltage at said first node and the output voltage of said summing circuit.

19. The voltage regulator of claim 18, wherein said power circuit comprises a pair of series-connected switches and an output inductor, said output inductor connected between the junction of said switches and said output node, and said fast voltage controller comprises a hysteretic comparator and a driving circuit, said driving circuit connected to control the states of said switches in accordance with a signal received at a control input, said comparator connected to receive the voltage at said first node and the output voltage of said summing circuit as inputs and producing an output connected to said driving circuit'"'"'s control input.

20. The voltage regulator of claim 19, wherein said impedance Z1 is implemented with a resistor R1 and a capacitor C1 connected in parallel, and impedance Z2 is implemented with a resistor R2, said resistors R1 and R2 and capacitor C1 arranged such that the output impedance of said voltage regulator is equal to R_e, whereby:

space="preserve" listing-type="equation">R2/R1=(R.sub.o -R.sub.s)/R.sub.s, and

space="preserve" listing-type="equation">C1*R1=C[(R.sub.o R.sub.e)/R.sub.s ].

21. The voltage regulator of claim 17, wherein said current sensor and summing circuit comprise a resistor having a resistance R_s connected between said controllable output stage at a second node and said output node, the voltage at said second node being said summing circuit output voltage.