Wafer-level burn-in and test

• US 6,064,213 A
• Filed: 01/15/1997
• Issued: 05/16/2000
• Est. Priority Date: 11/16/1993
• Status: Expired due to Term

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Khandros, Igor Y., Pedersen, David V.
• Primary Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US08/784,862
• Time in Patent Office: 1,217 Days
• Field of Search: 324/754, 324/757, 324/760, 324/761, 324/762, 324/765
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]

Abstract

Wafer-level burn-in and test of semiconductor devices under test (DUTs) includes a test substrate having active electronic components (e.g. ASICs) secured to an interconnection substrate, spring contact elements effecting interconnections between the ASICs and the DUTs. This is advantageously performed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs. The spring contact elements may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller.

Claims

1. A method for supporting wafer-level test of one or more semiconductor devices (DUTs) resident on a semiconductor wafer,

providing a semiconductor device (DUT) resident on a semiconductor wafer, the DUT having terminals,

providing an active electronic component having a surface and one or more terminals on the surface, the active electronic component connecting one or more test signals between the DUT and a test circuit;

providing a first plurality of spring contact elements between the DUT and the active electronic component, the spring contact elements of a size for chip scale connection, and

directly connecting one or more terminals of the DUT to a corresponding one or more terminals of the active electronic component through a corresponding one or more spring contact elements.

2. The method of claim 1 wherein:

a second plurality of the spring contact elements are mounted to the DUT.

3. The method of claim 1 wherein:

a second plurality of the spring contact elements are mounted to the active electronic component.

4. The method of claim 1 wherein:

a second plurality of the spring contact elements connecting the active electronic component to the DUT are mounted to an intermediary substrate.

5. The method of claim 1 wherein each of a second plurality of the spring contact elements comprises a free standing, resilient element, mounted to a first electronic component and in contact with a second electronic component, where the active electronic component and the DUT are respectively the first and second or second and first electronic component, the method further comprising connecting the free standing, resilient element to the second electronic component.

6. The method of claim 1 wherein the active electronic component makes selected electrical connection to the DUT and to no other DUT on the semiconductor wafer.

7. The method of claim 1 further comprising:

providing a plurality of DUTs on the semiconductor wafer;

providing a plurality of spring contact elements between the active electronic component and one or more corresponding terminals of a first plurality of the plurality of DUTs; and

connecting the active electronic component to one or more DUTs of the plurality of DUTs.

8. The method of claim 1 further comprising:

providing a first plurality of DUTs on the semiconductor wafer;

providing a first plurality of active electronic components;

providing a second plurality of spring contact elements between a second plurality of active electronic components and one or more corresponding terminals of a second plurality of the plurality of DUTs; and

connecting the second plurality of active electronic components to one or more DUTs of the second plurality of the plurality of DUTs.

9. The method of claim 8 further comprising providing a third plurality of active electronic components and a third plurality of spring contact elements and connecting substantially every DUT on the semiconductor wafer to at least one of the third plurality of active electronic components.

10. The method of claim 8 further comprising providing a third plurality of active electronic devices and a third plurality of spring contact elements and connecting substantially every DUT in a region of the semiconductor wafer to at least one of the third plurality of active electronic devices.

11. The method of claim 1 wherein:

the active electronic component is an ASIC.

12. The method of claim 1 further comprising:

selectively activating the active electronic component so as to test the DUT.

13. The method of claim 1 further comprising generating test information and delivering that test information through the active electronic component through the first plurality of spring contact elements to the DUT.

14. The method of claim 13 further comprising providing a test circuit in the active electronic device and connecting the test circuit to the DUT.

15. The method of claim 13 further comprising connecting a test circuit to the active electronic device and connecting the test circuit to the DUT.

16. The method of claim 13 further comprising collecting first test results from the response of the DUT and delivering the test results through the active electronic component.

17. The method of claim 1 further comprising:

providing a host controller; and

connecting the host controller to the active electronic component.

18. The method of claim 17, further comprising:

providing a first plurality of DUTs;

providing a first plurality of active electronic components;

providing common lines from the host controller to one or more of the first plurality of active electronic components, the number of common lines being fewer than the number of lines needed to make direct connection to one or more DUTs to be tested; and

providing test signals for testing the plurality of DUTs over the common lines.

19. The method of claim 18 further comprising testing one or more of the first plurality of DUTs to generate second test results, collecting the second test results and delivering the second test results to the host controller through the common lines.

20. The method of claim 11 further comprising:

providing a power supply; and

connecting the power supply to one or more of the active electronic components.

21. The method of claim 20 further comprising providing voltage regulation in the active electronic components.

22. The method of claim 1 wherein the terminals of the active electronic components are capture pads.

23. The method of claim 1 wherein the terminals of the electronic component are capture features.

24. The method of claim 1 further comprising mounting the active electronic components to an interconnection substrate.

25. The method of claim 1 performing a first test with the DUT at a first temperature and performing a second test with the DUT at a second temperature.

26. The method of claim 1 further comprising maintaining the active electronic component at a different temperature than the DUT.

27. The method of claim 1 wherein a spring contact element comprises a composite interconnection element.

28. The method of claim 1 further comprising aligning the active electronic device with the DUT before establishing a connection between them.

29. An apparatus for performing wafer-level test of one or more semiconductor devices (DUTs) resident on a semiconductor wafer,

a semiconductor device (DUT) resident on a semiconductor wafer, the DUT having terminals,

an active electronic component having a surface and one or more terminals on the surface, the active electronic component connecting one or more test signals between the DUT and a test circuit;

and

a first plurality of spring contact elements connecting the DUT and the active electronic component,

the spring contact elements of a size for chip scale connection,

each spring contact element directly connecting one or more terminals of the DUT to a corresponding one or more terminals of the active electronic component.

30. The apparatus of claim 29 wherein:

a second plurality of the spring contact elements are mounted to the DUT.

31. The apparatus of claim 30 wherein each of a third plurality of the spring contact elements comprises a free standing, resilient element, mounted to a first electronic component and in contact with a second electronic component, where the active electronic component and the DUT are respectively the first and second or second and first electronic component.

32. The apparatus of claim 29 wherein:

a second plurality of the spring contact elements are mounted to the active electronic component.

33. The apparatus of claim 29 wherein:

a second plurality of the spring contact elements connecting the active electronic component to the DUT are mounted to an intermediary substrate.

34. The apparatus of claim 29 wherein the active electronic component makes selected electrical connection to the DUT and to no other DUT on the semiconductor wafer.

35. The apparatus of claim 29 further comprising:

a plurality of DUTs on the semiconductor wafer; and

a second plurality of the spring contact elements between the active electronic component and one or more corresponding terminals of a first plurality of the plurality of DUTs.

36. The apparatus of claim 29 further comprising:

a first plurality of DUTs on the semiconductor wafer;

a first plurality of active electronic components; and

a second plurality of spring contact elements, each spring contact element connecting a one of the first plurality of active electronic components and one or more corresponding terminals of a one of the first plurality of DUTs.

37. The apparatus of claim 36 further comprising a plurality of active electronic devices connected to substantially every DUT on the semiconductor wafer.

38. The apparatus of claim 36 further comprising a plurality of active electronic devices connected to substantially every DUT in a region of the semiconductor wafer.

39. The apparatus of claim 29 wherein:

the active electronic component is an ASIC.

40. The apparatus of claim 29 further comprising:

means for selectively activating the active electronic component so as to test a selected one or more of the DUTs.

41. The apparatus of claim 29 further comprising a test information source and means for delivering test information from that test information source through the active electronic component through the spring contact elements to the DUT.

42. The apparatus of claim 41 further comprising a test circuit in the active electronic device.

43. The apparatus of claim 41 further comprising a test circuit connected to the active electronic device.

44. The apparatus of claim 41 further comprising a test result collector for collecting test results from the response of a DUT and a test delivery mechanism for delivering the test results through the active electronic component.

45. The apparatus of claim 29 further comprising:

a host controller; and

the host controller connected to the active electronic component.

46. The apparatus of claim 45, further comprising:

a plurality of active electronic components; and

common lines connecting the host controller to one or more active electronic components, the number of common lines being fewer than the number of lines that would be needed to make direct connection to one or more DUTs to be tested.

47. The apparatus of claim 46 further comprising:

means for communicating test signals over the common lines to the one or more active electronic devices; and

means for delivering second test results to the host controller through the common lines.

48. The apparatus of claim 29 further comprising:

a power supply; and

the power supply connected to one or more of the active electronic components.

49. The apparatus of claim 48 further comprising voltage regulation means in the active electronic components.

50. The apparatus of claim 29 wherein the terminals of the active electronic components are capture pads.

51. The apparatus of claim 29 wherein the terminals of the electronic component are capture features.

52. The apparatus of claim 29 further comprising an interconnection substrate wherein the active electronic components are mounted to the interconnection substrate.

53. The apparatus of claim 29 further comprising temperature modification means for providing a first and a second temperature for a DUT in operation.

54. The apparatus of claim 29 further comprising means for maintaining the active electronic component at temperature independent of the temperature of the DUT.

55. The apparatus of claim 29 wherein a spring contact element comprises a composite interconnection element.

56. The apparatus of claim 29 further comprising an aligning mechanism for aligning the active electronic device with the DUT.