Apparatus for testing semiconductor wafers
First Claim
1. An apparatus for testing a semiconductor wafer comprising:
- a base configured to retain the wafer;
an electrical connector on the base configured for electrical communication with external circuitry;
an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a raised portion of the substrate and a conductive layer at least partially covering the raised portion;
a tape on the substrate comprising a dielectric layer and a trace layer on the dielectric layer having a via therethrough proximate to the contact member; and
a conductive material within the via electrically connecting the conductive layer to the trace layer.
7 Assignments
0 Petitions
Accused Products
Abstract
A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
-
Citations
20 Claims
-
1. An apparatus for testing a semiconductor wafer comprising:
-
a base configured to retain the wafer; an electrical connector on the base configured for electrical communication with external circuitry; an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a raised portion of the substrate and a conductive layer at least partially covering the raised portion; a tape on the substrate comprising a dielectric layer and a trace layer on the dielectric layer having a via therethrough proximate to the contact member; and a conductive material within the via electrically connecting the conductive layer to the trace layer. - View Dependent Claims (2, 3, 4, 5)
-
-
6. An apparatus for testing a semiconductor wafer comprising:
-
a base; a cover attached to the base, the cover and the base configured to retain the wafer therebetween; an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer and having a height, the contact member comprising at least one projection configured to penetrate the contact location and a conductive layer at least partially covering the projection; a tape on the substrate having a thickness, the tape comprising a dielectric layer and a trace layer on the dielectric layer having a via therethrough proximate to the contact member, with the thickness of the tape less than the height of the contact member such that the projection is exposed for penetrating the contact location; and a conductive material within the via electrically connecting the conductive layer to the trace layer. - View Dependent Claims (7, 8, 9, 10)
-
-
11. An apparatus for testing a semiconductor wafer comprising:
-
a base; a cover attached to the base, the cover and the base configured to retain the wafer therebetween; an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a portion of the substrate and a conductive layer at least partially covering the portion; and a tape on the substrate comprising a polyimide layer and a trace layer on the polyimide layer in electrical communication with the conductive layer on the contact member. - View Dependent Claims (13, 14, 15)
-
-
12. The apparatus of claim further comprising a first elastomeric spring between the wafer and the cover for biasing the wafer against the interconnect together.
-
16. An apparatus for testing a semiconductor wafer comprising:
-
a base; a cover attached to the base, the cover and the base configured to retain the wafer therebetween; an electrical connector on the base configured for electrical communication with external circuitry; a spring member between the cover and the base configured to bias the wafer against the interconnect; an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a portion of the substrate and a conductive layer at least partially covering the portion; and a tape on the substrate comprising a dielectric layer, a trace layer on the dielectric layer in electrical communication with the conductive layer and with the electrical connector, and a ground layer on the dielectric layer for adjusting an impedance of the trace layer. - View Dependent Claims (17, 18, 19, 20)
-
Specification