Apparatus for testing semiconductor wafers

• US 6,064,216 A
• Filed: 02/01/1999
• Issued: 05/16/2000
• Est. Priority Date: 12/31/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Hembree, David R., Wark, James M., Wood, Alan G., Akram, Salman, Jacobson, John O.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US09/241,553
• Time in Patent Office: 470 Days
• Field of Search: 324/754, 324/755, 324/761, 324/762, 324/765, 438/14, 438/17, 438/18, 257/40, 257/48
• US Class Current: 324/756.05
• CPC Class Codes: G01R 1/0491 for testing integrated circuits on wafers, e.g. wafer-level test cartridge
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.

Claims

1. An apparatus for testing a semiconductor wafer comprising:

a base configured to retain the wafer;

an electrical connector on the base configured for electrical communication with external circuitry;

an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a raised portion of the substrate and a conductive layer at least partially covering the raised portion;

a tape on the substrate comprising a dielectric layer and a trace layer on the dielectric layer having a via therethrough proximate to the contact member; and

a conductive material within the via electrically connecting the conductive layer to the trace layer.

2. The apparatus of claim 1 wherein the contact member comprises a projection configured to penetrate the contact location.

3. The apparatus of claim 1 further comprising a ground layer on the tape for adjusting an impedance of the trace layer.

4. The apparatus of claim 1 wherein the dielectric layer comprises polyimide.

5. The apparatus of claim 1 wherein a thickness of the tape is less than a height of the contact member.

6. An apparatus for testing a semiconductor wafer comprising:

a base;

a cover attached to the base, the cover and the base configured to retain the wafer therebetween;

an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer and having a height, the contact member comprising at least one projection configured to penetrate the contact location and a conductive layer at least partially covering the projection;

a tape on the substrate having a thickness, the tape comprising a dielectric layer and a trace layer on the dielectric layer having a via therethrough proximate to the contact member, with the thickness of the tape less than the height of the contact member such that the projection is exposed for penetrating the contact location; and

a conductive material within the via electrically connecting the conductive layer to the trace layer.

7. The apparatus of claim 6 wherein the conductive material comprises a conductive adhesive.

8. The apparatus of claim 6 wherein the substrate comprises silicon and the contact member comprises an etched portion of the substrate.

9. The apparatus of claim 6 wherein the contact location comprises a pad.

10. The apparatus of claim 6 wherein the contact location comprises a bump.

11. An apparatus for testing a semiconductor wafer comprising:

a base;

a cover attached to the base, the cover and the base configured to retain the wafer therebetween;

an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a portion of the substrate and a conductive layer at least partially covering the portion; and

a tape on the substrate comprising a polyimide layer and a trace layer on the polyimide layer in electrical communication with the conductive layer on the contact member.

13. The apparatus of claim 11 further comprising a second elastomeric spring between the interconnect and the base for biasing the interconnect against the wafer.

14. The apparatus of claim 11 further comprising a ground layer on the tape for adjusting an impedance of the trace layer.

15. The apparatus of claim 11 wherein the contact member comprises a projection configured to penetrate the contact location to a limited penetration depth.

12. The apparatus of claim further comprising a first elastomeric spring between the wafer and the cover for biasing the wafer against the interconnect together.

16. An apparatus for testing a semiconductor wafer comprising:

a base;

a cover attached to the base, the cover and the base configured to retain the wafer therebetween;

an electrical connector on the base configured for electrical communication with external circuitry;

a spring member between the cover and the base configured to bias the wafer against the interconnect;

an interconnect on the base comprising a substrate and a contact member on the substrate configured to electrically contact a contact location on the wafer, the contact member comprising a portion of the substrate and a conductive layer at least partially covering the portion; and

a tape on the substrate comprising a dielectric layer, a trace layer on the dielectric layer in electrical communication with the conductive layer and with the electrical connector, and a ground layer on the dielectric layer for adjusting an impedance of the trace layer.

17. The apparatus of claim 16 wherein the base comprises a first cavity wherein the interconnect is mounted.

18. The apparatus of claim 16 wherein the spring member comprises a first elastomeric pad between the cover and the wafer.

19. The apparatus of claim 16 wherein the spring member comprises a second elastomeric pad between the wafer and the base.

20. The apparatus of claim 16 wherein the portion comprises a raised portion and the contact location comprises a pad.